WJLXT384LE.B1-868635 Cortina Systems Inc, WJLXT384LE.B1-868635 Datasheet - Page 25

• Manufacturer Part Number: WJLXT384LE.B1-868635
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT384LE.B1-868635

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

LXT384 Transceiver
Datasheet
248994, Revision 6.0
30 January 2008
Table 6
5.3
5.3.1
Cortina Systems
Microprocessor-Standard Bus and Interface Signals (Sheet 3 of 3)
Framer/Mapper Signals
Framer/mapper signals are used to interface the LXT384 Transceiver to a framer/mapper.
Bipolar vs. Unipolar Operation - Receive Side
either bipolar or unipolar interface connections.
Depending on the state of a UBS7:0 pin, both the corresponding receiver and transmitter
pins are automatically set for either bipolar I/O or unipolar I/O. When a UBS pin is
connected:
Receive side - Bipolar I/O. When TNEG/UBS is connected low, then bipolar I/O is selected
and RNEG/RPOS functions are selected. In this case, the signal flow occurs as follows:
®
lists receive-side framer/mapper signals, which can connect to a framer/mapper using
1. DI: Digital Input. DI/O: Digital Bidirectional Port. DO: Digital Output. OD: Open Drain
DS /
DS / SDI / WR/
1. The receiver routes receive analog signals from RTIP/RRING to a data recovery circuit.
2. The data recovery circuit converts the incoming line AMI signals, which consist of
3. The recovered clock from RTIP/RRING is output at RCLK.
SCLK/LEN2
ACK / RDY /
• Low, bipolar I/O is selected.
• High for more than 16 consecutive MCLK clock cycles, unipolar I/O is selected.
LXT384 Octal T1/E1/J1 Short-Haul PCM Transceiver with Jitter Attenuation (JA)
ALE / AS /
positive and negative pulses, into a sequence of logic zeroes and ones. It then outputs
the resulting information onto RNEG and RPOS.
LEN0
LEN0
SDI
SDO
/ WR/
86
84
83
84
K14
J12
J14
J14
DO
DI
DI
DI
Shift Clock Input.
When SCLK is in the:
For other pin functions, see AS and ALE.
Serial Data Input.
When the LXT384 Transceiver is in the:
For other pin functions, see DS and WR.
Serial Data Output.
When the LXT384 Transceiver is in the Host Processor mode
using a serial interface and the signal on CLKE is:
Note:
For other pin functions, see ACK and RDY.
Write Enable Input.
When the LXT384 Transceiver is in:
For other pin functions, see DS and SDI.
• Host Processor mode using a serial interface, SCLK acts as
• Hardware mode, SCLK must be connected to ground.
• Host Processor mode using a serial interface, SDI is used as
• Hardware mode, SDI must be connected to ground.
• Low, SDO is valid on the falling edge of SCLK.
• High, SDO is valid on the rising edge of SCLK.
• Host Processor mode using an Intel* processor, WR acts as
• Hardware mode, WR must be connected to ground.
a serial shift clock.
serial data input.
a write enable.
SDO goes into a high-impedance tristate during a serial
port write access.
Table 7
TM
TM
lists details.
5.3 Framer/Mapper Signals
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