WJLXT384LE.B1-868635 Cortina Systems Inc, WJLXT384LE.B1-868635 Datasheet - Page 38

• Manufacturer Part Number: WJLXT384LE.B1-868635
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT384LE.B1-868635

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

LXT384 Transceiver
Datasheet
248994, Revision 6.0
30 January 2008
Table 11
Cortina Systems
Configuration and Mode-Select Signals (Sheet 1 of 2)
®
1. DI: Digital Input
CODEN
CODEN /
LXT384 Octal T1/E1/J1 Short-Haul PCM Transceiver with Jitter Attenuation (JA)
CS /
CS
Signal
Name
MOT
MOT
/ JASEL
JASEL
/ INTL /
INTL
/
QFP
Pin
88
88
87
87
PBGA
Ball
H12
H12
J11
J11
I/O
DI
DI
DI
DI
1
Codec Enable Select Input.
When the LXT384 Transceiver is in the Hardware mode, CODEN
determines the line encoder/decoder selection when in unipolar
mode. When CODEN is:
Note:
For other pin functions, see INTL/MOT.
Host Processor Select Input.
When the LXT384 Transceiver is in the host processor mode and
this signal is:
For other pin functions, see CODEN.
Chip Select Input.
In Host Mode, this active Low input is used to access the serial/
parallel interface. For each read or write operation, CS must
transition from High to Low, and remain Low.
For information on the CS signal, see
Standard Bus and Interface
Jitter Attenuator Select Input.
When the LXT384 Transceiver is in the Hardware mode, JASEL
determines the jitter attenuator (JA) position, as listed in the
following table.
For other pin functions, see CS in
Standard Bus and Interface
Low
High
High impedance
• Low, it enables an HDB3 encoder/decoder for E1 or a B8ZS
• High, it enables an AMI encoder/decoder (transparent mode).
• high, the host processor interface is configured for Intel*
• low, the host processor interface is configured for Motorola
encoder/decoder for T1.
microcontrollers.
microcontrollers.
In the host processor mode, the encoding/decoding type is
determined by the CODEN bit. (For CODEN bit details, see
Section 8.0,
JASEL
Registers.)
TM
TM
Signal Description
Transmit path
Receive path
JA is disabled
Signals.
Signals.
5.6 Configuration and Mode-Select
JA Position
Section 5.2, Microprocessor-
Section 5.2, Microprocessor-
Page 38
Signals