WJLXT384LE.B1-868635 Cortina Systems Inc, WJLXT384LE.B1-868635 Datasheet - Page 66

• Manufacturer Part Number: WJLXT384LE.B1-868635
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT384LE.B1-868635

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

LXT384 Transceiver
Datasheet
248994, Revision 6.0
30 January 2008
Note:
7.4.1.1
7.4.2
Cortina Systems
When an Intel* processor is used with a non-multiplexed interface, there is one exception to
how write-cycle timing operates that involves the use of Register 0Ah, the reset register. At
the start of the write cycle, the RDY line remains high instead of signaling the completion of
the write cycle with a transition to a low state. The overall duration of the reset cycle from
when the signal on CS is low to the completion of the reset cycle is a total of 3
microseconds. As a result, upon writing to Register 0Ah, allow a minimum of 2
microseconds of constant throughput delay before attempting the next read/write operation.
(For more information on the reset cycle, see
Descriptions.)
Host Processor Mode - Parallel Interface, Intel* Processor
The Intel* processor interface is selected by asserting the LXT384 Transceiver MOT/INTL
pin high. Both the read and write cycles require CS to be low. When the Intel* processor
attempts to:
The LXT384 Transceiver supports a:
Host Processor Mode - Serial Interface
A Host Processor mode with a serial interface consisting of the CS, SCLK, SDI, and SDO
pins is selected by connecting the MODE pin to a voltage that is equal to 1/2 VCC (which
can be accomplished by connecting one 10 kΩ resistor to VCC and a second 10 kΩ resistor
to ground).
Figure 14
are accessible through a 16-bit word consisting of the following:
®
• Intel* processor and RDY is:
• Read data from the LXT384 Transceiver, it asserts RD low while WR is held high.
• Write data to the LXT384 Transceiver, it asserts WR low while RD is held high.
• Non-multiplexed Intel* processor parallel interface when MUX is asserted low. In
• Multiplexed Intel* processor parallel interface when MUX is asserted high. In the
• An 8-bit Address/Command byte.
• A subsequent 8-bit Data byte. (Depending on the R/W state, the D0-D7 values are valid
LXT384 Octal T1/E1/J1 Short-Haul PCM Transceiver with Jitter Attenuation (JA)
— Write cycle, ACK indicates the LXT384 Transceiver has accepted the write data
— Low, the LXT384 Transceiver indicates to the Intel* processor a bus cycle is in
nonmultiplexed mode, ALE must be connected high and the address and data lines are
separate.
multiplexed mode, the falling edge of ALE latches the address.
— The signal on the R/W pin determines whether a read or a write operation occurs.
— The signals on pins A1-A5 go to an address decoder that decodes an address.
on either SDI or SDO, but never are the D0-D7 values valid on both SDI and SDO.)
— When R/W = 0, D0-D7 on SDO are don’t cares. The D0-D7 values on SDI are
— When R/W = 1, the D0-D7 values on SDO are active, with valid data that the
from the Motorola* processor.
progress.
(The address decoder ignores signals on the A6 and A7 pins.)
active, with valid data being written to the LXT384 Transceiver.
LXT384 Transceiver writes to the host processor. The D0-D7 values on SDI are
don’t cares.
shows timing for the host processor interface when it is in serial mode. Registers
Table 37
TM
TM
in
Section 8.3, Register
7.4 Host Processor Modes
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