WJLXT384LE.B1-868635 Cortina Systems Inc, WJLXT384LE.B1-868635 Datasheet - Page 99

• Manufacturer Part Number: WJLXT384LE.B1-868635
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT384LE.B1-868635

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

LXT384 Transceiver
Datasheet
248994, Revision 6.0
30 January 2008
Table 66
Cortina Systems
Intel*
Figure 21
non- multiplexed interface, and a read cycle takes place.
®
Address setup time to latch
Valid address latch pulse width
Latch active to active read setup time
Chip select setup time to active read
Chip select hold time from inactive read
Address hold time from inactive ALE
Active read to data valid delay time
Address setup time to RD inactive
Address hold time from RD inactive
Inactive read to data high-impedance tristate delay
time
Valid read signal pulse width
Inactive read to inactive INT delay time
Active chip select to RDY delay time
Active ready low time
Inactive ready to high-impedance tristate delay
time
1. Minimum and maximum values are at 25
LXT384 Octal T1/E1/J1 Short-Haul PCM Transceiver with Jitter Attenuation (JA)
production testing.
Processor - Read Timing Characteristics
is a timing diagram for the Intel* processor in the Host Processor mode, with a
Parameter
o
C and are for design aid only, not guaranteed, and not subject to
Sym.
t
t
t
t
t
t
t
HSCR
DRDY
t
SCSR
HALR
t
t
t
t
t
VRDY
RDYZ
SALR
t
PRD
HAR
VRD
t
SLR
SAR
ZRD
INT
VL
Min.
10
30
10
10
60
0
0
5
1
5
3
–
0
–
–
TM
TM
1
11.2 Host Processor Mode - Parallel
Max.
50
35
10
12
40
–
–
–
–
–
–
–
–
3
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
on D7:0.
All other outputs
are loaded with
50 pF.
Interface Timing
Load
Conditions
Test
= 100 pF
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