WJLXT384LE.B1-868635 Cortina Systems Inc, WJLXT384LE.B1-868635 Datasheet - Page 39

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WJLXT384LE.B1-868635

Manufacturer Part Number
WJLXT384LE.B1-868635
Description
Manufacturer
Cortina Systems Inc
Datasheet

Specifications of WJLXT384LE.B1-868635

Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
WJLXT384LE.B1-868635
Manufacturer:
INTEL
Quantity:
20 000
LXT384 Transceiver
Datasheet
248994, Revision 6.0
30 January 2008
Table 11
5.7
Cortina Systems
Configuration and Mode-Select Signals (Sheet 2 of 2)
Signal Loss and Line-Code-Violation Signals
Table 12
®
1. DI: Digital Input
TNEG7 /
TNEG6 /
TNEG5 /
TNEG4 /
TNEG3 /
TNEG2 /
TNEG1 /
TNEG0 /
LXT384 Octal T1/E1/J1 Short-Haul PCM Transceiver with Jitter Attenuation (JA)
Signal
MODE
Name
MUX
UBS7
UBS6
UBS5
UBS4
UBS3
UBS2
UBS1
UBS0
lists and the signal loss and line-code violation signals for the LXT384 Transceiver.
QFP
144
102
109
Pin
43
72
79
31
38
11
7
PBGA
Ball
D12
N12
B12
L12
E2
K2
B3
D3
N3
L3
I/O
DI
DI
DI
1
Mode Select Input.
MODE is used to select the type of operating mode the
LXT384 Transceiver uses, as shown in the following table.
Note:
For details on modes in the table, see the following:
Multiplexed/Non-Multiplexed Select Input.
When the LXT384 Transceiver is in parallel interface host processor
mode, and MUX is:
In hardware mode, tie this unused input low.
For timing diagrams, see
Unipolar/Bipolar Select Input 7:0.
For information on the UBS signals, see
Mapper
Low
High
VCC/2
Parallel Interface
• In Hardware Mode (low), the parallel processor interface is
• In Parallel Host Mode (high), the parallel port interface pins are
• In Serial Host mode (VCC/2), the serial interface pins: SDI,
• Low, operation is in non-multiplexed mode.
• High, operation is in multiplexed mode.
disabled and hard-wired pins are used to control configuration
and report status.
used to control configuration and report status.
SDO, SCLK, and CS are used.
Section 7.2, Hardware Mode
Section 7.4.1, Host Processor Mode - Parallel Interface
Section 7.4.2, Host Processor Mode - Serial Interface
MODE
Signals.
VCC/2 can be obtained by connecting to a resistive divider
consisting of two 10 k Ω resistors across V
Hardware mode
Host Processor mode – Parallel
interface
Host Processor mode – Serial interface
Timing.
TM
TM
Signal Description
Section 11.2, Host Processor Mode -
Operating Mode
5.7 Signal Loss and Line-Code-
Section 5.3, Framer/
Violation Signals
CC
and Ground.
Page 39

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