PSD935G2-90U STMicroelectronics, PSD935G2-90U Datasheet - Page 10

• Manufacturer Part Number: PSD935G2-90U
• Manufacturer: STMicroelectronics

Specifications of PSD935G2-90U

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: TQFP
• Mounting: Surface Mount
• Pin Count: 80
• Lead Free Status / RoHS Status: Compliant

PSD935G2
Table 5.
PSD935G2
Pin
Descriptions
(cont.)
PA0-PA7 51-58
PB0-PB7 61-68
PC0-PC7 41-48
PD0
PD1
PD2
PD3
PE0
PE1
PE2
Pin Name Pkg.)
(TQFP
Pin*
79
80
71
72
73
1
2
or Open 1. MCU I/O — standard output or input port
or Open 1. MCU I/O — standard output or input port.
or Open 2. AS input — latches addresses on ADIO0-15 pins on the
or Open 2. Input to the PLD.
or Open 2. Input to the PLD.
or Open
or Open 1. MCU I/O — standard output or input port.
or Open 1. MCU I/O — standard output or input port.
or Open 1. MCU I/O — standard output or input port.
or Slew
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Drain
Drain
Drain
Drain
Drain
Drain
Drain
Drain
Drain
Rate
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port A, PA0-7. This port is pin configurable and has multiple
functions:
2. GPLD output.
3. Input to the PLD.
Port B, PB0-7. This port is pin configurable and has multiple
functions:
2. GPLD output.
3. Input to the PLD.
Port C, PC0-7. This port is pin configurable and has multiple
functions:
1. MCU I/O — standard output or input port.
2. External chip select (ECS0-7) output.
3. Input to the PLD.
Port D pin PD0 can be configured as:
1. ALE or AS input — latches addresses on ADIO0-15 pins
3. Input to the PLD.
4. Transparent PLD input.
Port D pin PD1 can be configured as:
1. MCU I/O
3. CLKIN clock input — clock input to the GPLD
Port D pin PD2 can be configured as:
1. MCU I/O
3. CSI input — chip select input. When low, the CSI enables
Port D pin PD3 can be configured as:
1. MCU I/O
2. Input to the PLD.
Port E, PE0. This port is pin configurable and has multiple
functions:
2. Latched address output.
3. TMS input for JTAG/ISP interface.
Port E, PE1. This port is pin configurable and has multiple
functions:
2. Latched address output.
3. TCK input for JTAG/ISP interface (Schmidt Trigger).
Port E, PE2. This port is pin configurable and has multiple
functions:
2. Latched address output.
3. TDI input for JTAG/ISP interface.
rising edge.
Micro Cells, the APD power down counter and GPLD
AND Array.
the internal PSD memories and I/O. When high, the
internal memories are disabled to conserve power. CSI
trailing edge can get the part out of power-down mode.
Description
PSD9XX Family
9