PSD935G2-90U STMicroelectronics, PSD935G2-90U Datasheet - Page 22

• Manufacturer Part Number: PSD935G2-90U
• Manufacturer: STMicroelectronics

Specifications of PSD935G2-90U

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: TQFP
• Mounting: Surface Mount
• Pin Count: 80
• Lead Free Status / RoHS Status: Compliant

PSD935G2
The
PSD935G2
Functional
Blocks
(cont.)
9.1.1.7 Programming Flash Memory
Flash memory must be erased prior to being programmed. The MCU may erase Flash
memory all at once or by-sector. Flash memory sector erases to all logic ones (FF hex),
and its bits are programmed to logic zeros. Although erasing Flash memory occurs on a
sector basis, programming Flash memory occurs on a word basis.
The PSD935G2 main Flash and secondary Flash memories require the MCU to send an
instruction to program a word or perform an erase function (see Table 8).
Once the MCU issues a Flash memory program or erase instruction, it must check for the
status of completion. The embedded algorithms that are invoked inside the PSD935G2
support several means to provide status to the MCU. Status may be checked using any of
three methods: Data Polling, Data Toggle, or the Ready/Busy output pin.
9.1.1.7.1 Data Polling
Polling on DQ7 is a method of checking whether a Program or Erase instruction is in
progress or has completed. Figure 4 shows the Data Polling algorithm.
When the MCU issues a programming instruction, the embedded algorithm within the
PSD935G2 begins. The MCU then reads the location of the word to be programmed in
Flash to check status. Data bit DQ7 of this location becomes the compliment of data
bit 7of the original data word to be programmed. The MCU continues to poll this location,
comparing DQ7 and monitoring the Error bit on DQ5. When the DQ7 matches data bit 7 of
the original data, and the Error bit at DQ5 remains ‘0’, then the embedded algorithm is
complete. If the Error bit at DQ5 is ‘1’, the MCU should test DQ7 again since DQ7 may
have changed simultaneously with DQ5 (see Figure 4).
The Error bit at DQ5 will be set if either an internal timeout occurred while the embedded
algorithm attempted to program the location or if the MCU attempted to program a ‘1’ to a
bit that was not erased (not erased is logic ‘0’).
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed to compare the word that was written to Flash with
the word that was intended to be written.
When using the Data Polling method after an erase instruction, Figure 4 still applies.
However, DQ7 will be ‘0’ until the erase operation is complete. A ‘1’ on DQ5 will indicate
a timeout failure of the erase operation, a ‘0’ indicates no error. The MCU can read any
location within the sector being erased to get DQ7 and DQ5.
PSDsoft generates ANSI C code functions which implement these Data Polling
algorithms.
PSD9XX Family
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