PSD935G2-90U STMicroelectronics, PSD935G2-90U Datasheet - Page 62

• Manufacturer Part Number: PSD935G2-90U
• Manufacturer: STMicroelectronics

Specifications of PSD935G2-90U

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: TQFP
• Mounting: Surface Mount
• Pin Count: 80
• Lead Free Status / RoHS Status: Compliant

PSD935G2
The
PSD935G2
Functional
Blocks
(cont.)
9.5.3.4 Reset of Flash Erase and Programming Cycles
An external reset on the RESET pin will also reset the internal Flash memory state
machine. When the Flash is in programming or erase mode, the RESET pin will terminate
the programming or erase operation and return the Flash back to read mode in tNLNH-A
(minimum 25 µs) time.
9.6 Programming In-Circuit using the JTAG-ISP Interface
The JTAG-ISP interface on the PSD935G2 can be enabled on Port E (see Table 29). All
memory (Flash and Flash Boot Block), PLD logic, and PSD configuration bits may be
programmed through the JTAG-ISC interface. A blank part can be mounted on a printed
circuit board and programmed using JTAG-ISP.
The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional
signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and
erase operations.
Table 28. Status During Power On Reset, Warm Reset and Power Down Mode
*
See ST Application Note AN1153 for more details on JTAG In-System-Programming.
Table 29. JTAG Port Signals
Port Configuration
SR_cod bit in the VM Register are always cleared to zero on power on or warm reset.
By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port E
are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.
PMMR0, 2
VM Register*
All other registers
Port E Pin
MCU I/O
PLD Output
Address Out
Data Port
Register
PE0
PE1
PE2
PE3
PE4
PE5
JTAG Signals
TSTAT
Input Mode
Valid after internal
PSD configuration
bits are loaded
Tri-stated
Tri-stated
Cleared to “0”
Initialized based on
the selection in
PSDsoft
Configuration Menu.
Cleared to “0”
TERR
TMS
TDO
TCK
TDI
Power On Reset
Power On Reset
Mode Select
Clock
Serial Data In
Serial Data Out
Status
Error Flag
Description
Unchanged
Initialized based on
the selection in
PSDsoft
Configuration Menu.
Cleared to “0”
Warm Reset
Warm Reset
Input Mode
Valid
Tri-stated
Tri-stated
PSD9XX Family
Power Down Mode
Unchanged
Depend on inputs to
PLD (address are
blocked in PD mode)
Not defined
Tri-stated
Unchanged
Unchanged
Unchanged
Power Down Mode
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