PSD935G2-90U STMicroelectronics, PSD935G2-90U Datasheet - Page 59

• Manufacturer Part Number: PSD935G2-90U
• Manufacturer: STMicroelectronics

Specifications of PSD935G2-90U

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: TQFP
• Mounting: Surface Mount
• Pin Count: 80
• Lead Free Status / RoHS Status: Compliant

The
PSD935G2
Functional
Blocks
(cont.)
58
PSD9XX Family
Table 26. Power Management Mode Registers (PMMR0, PMMR2)**
PMMR0
***
***
***
Bit 1 0 = Automatic Power Down (APD) is disabled.
Bit 3 0 = PLD Turbo is on.
Bit 4 0 = CLKIN input to the PLD AND array is connected.
PMMR2
**
**
Bit 0 0 = Address A[7:0] inputs to the PLD AND array are connected.
Bit 2 0 = Cntl0 input to the PLD AND array is connected.
Bit 3 0 = Cntl1 input to the PLD AND array is connected.
Bit 4 0 = Cntl2 input to the PLD AND array is connected.
Bit 5 0 = ALE input to the PLD AND array is connected.
Bit 6 0 = DBE input to the PLD AND array is connected.
Unused bits should be set to 0.
Refer to Table 14 the signals that are blocked on pins CNTL0-2.
Bits 0, 2, 6, and 7 are not used, and should be set to 0, bit 5 should be set to 1.
The PMMR0, and PMMR2 register bits are cleared to zero following power up.
Subsequent reset pulses will not clear the registers.
Bit 7
Bit 7
*
*
1 = Automatic Power Down (APD) is enabled.
1 = PLD Turbo is off, saving power.
1 = CLKIN input to PLD AND array is disconnected, saving power.
1 = Address A[7:0] inputs to the PLD AND array are disconnected, saving power.
1 = Cntl0 input to PLD AND array is disconnected, saving power.
1 = Cntl1 input to PLD AND array is disconnected, saving power.
1 = Cntl2 input to PLD AND array is disconnected, saving power.
1 = ALE input to PLD AND array is disconnected, saving power.
1 = DBE input to PLD AND array is disconnected, saving power.
Every CLKIN change will power up the PLD when Turbo bit is off.
Note: In 80C51XA mode, A[7:1] comes from Port F (PF1-PF3) and AD10 [3:0].
1 = off
Bit 6
Bit 6
array
DBE
PLD
*
1 = off
Bit 5
Bit 5
array
PLD
ALE
*
Array clk
1 = off
CNTL2
PLD
1 = off
Bit 4
Bit 4
PLD
array
**
1 = off
CNTL1
Turbo
1 = off
PLD
Bit 3
Bit 3
PLD
array
**
CNTL0
PLD
1 = off
Bit 2
Bit 2
array
*
**
PSD935G2
Enable
1 = on
Bit 1
APD
Bit 1
*
1 = off
Bit 0
Bit 0
Addr.
array
PLD
*