PSD935G2-90U STMicroelectronics, PSD935G2-90U Datasheet - Page 4

• Manufacturer Part Number: PSD935G2-90U
• Manufacturer: STMicroelectronics

Specifications of PSD935G2-90U

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: TQFP
• Mounting: Surface Mount
• Pin Count: 80
• Lead Free Status / RoHS Status: Compliant

PSD935G2
2.0
Key Features
Table 1. PSD9XX Product Matrix
3.0 PSD9XX
Series
PSD9XX
PSD9XX
Part #
Series
PSD935G2
PSD913G2
PSD934F2
Device
Pins
I/O
52
27
27
A simple interface to 8-bit microcontrollers that use either multiplexed or
non-multiplexed busses. The bus interface logic uses the control signals generated by
the microcontroller automatically when the address is decoded and a read or write is
performed. A partial list of the MCU families supported include:
•
•
•
•
•
4 Mbit Flash memory. This is the main Flash memory. It is divided into eight
equal-sized blocks that can be accessed with user-specified addresses.
Internal secondary 256 Kbit Flash boot memory. It is divided into four equal-sized
blocks that can be accessed with user-specified addresses. This secondary memory
brings the ability to execute code and update the main Flash concurrently.
64 Kbit SRAM. The SRAM’s contents can be protected from a power failure by
connecting an external battery.
General Purpose PLD (GPLD) with 24 outputs. The GPLD may be used to implement
external chip selects or combinatorial logic function.
Decode PLD (DPLD) that decodes address for selection of internal memory blocks.
52 individually configurable I/O port pins that can be used for the following functions:
•
•
•
•
•
Standby current as low as 50 µA for 5 V devices.
Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP).
With it, you can program a blank device or reprogram a device in the factory or the field.
Internal page register that can be used to expand the microcontroller address space
by a factor of 256.
Internal programmable Power Management Unit (PMU) that supports a low power
mode called Power Down Mode. The PMU can automatically detect a lack of
microcontroller activity and put the PSD9XX into Power Down Mode.
Erase/Write cycles:
•
•
Flash memory – 100,000 minimum
PLD – 1,000 minimum
Intel 8031, 80196, 80188, 80C251
Motorola 68HC11 and 68HC16
Philips 8031 and 80C51XA
Zilog Z80, Z8 and Z180
Infineon C500 family
MCU I/Os
PLD I/Os
Latched MCU address output
Special function I/Os.
I/O ports may be configured as open-drain outputs.
Inputs Macrocells Macrocells Outputs
PLD
66
57
57
Input
Output
PLD
24
19
19
Serial ISP
JTAG/ISP
Flash
Port
Yes
Yes
Yes
8 Sectors (4 Sectors)
Memory
Flash
4096
1024
2048
Main
Kbit
PSD9XX Family
Memory
Boot
Kbit
256
256
256
SRAM
Kbit
64
16
64
Voltage
Supply
5V
5V
5V
3