PSD935G2-90U STMicroelectronics, PSD935G2-90U Datasheet - Page 54

• Manufacturer Part Number: PSD935G2-90U
• Manufacturer: STMicroelectronics

Specifications of PSD935G2-90U

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: TQFP
• Mounting: Surface Mount
• Pin Count: 80
• Lead Free Status / RoHS Status: Compliant

PSD935G2
The
PSD935G2
Functional
Blocks
(cont.)
9.4.6 Port D – Functionality and Structure
Port D has four I/O pins. See Figure 22. Port D can be configured to program one or more
of the following functions:
Port D pins can be configured in PSDsoft as input pins for other dedicated functions:
9.4.7 Port E – Functionality and Structure
Port E can be configured to perform one or more of the following functions (see Figure 23):
Figure 22. Port D Structure
MCU I/O Mode
PLD Input – direct input to PLD
PD0 – ALE, as address strobe input
PD1 – CLKIN, as clock input to the PLD and APD counter
PD2 – CSI, as active low chip select input. A high input will disable the
Flash/SRAM and CSIOP.
PD3 – DBE input from 68HC912
MCU I/O Mode
In-System Programming – JTAG port can be enabled for programming/erase of the
PSD935G2 device. (See Section 9.6 for more information on JTAG programming.)
Pins that are configured as JTAG pins in PSDsoft will not be available for other I/O
functions.
Open Drain – Port E pins can be configured in Open Drain Mode
Battery Backup features – PE6 can be configured as a Battery Input (Vstby) pin.
Latched Address Output – Provided latched address (A7-0) output
WR
WR
READ MUX
DATA OUT
DIR REG.
D
D
REG.
D
B
P
Q
Q
PE7 can be configured as a Battery On Indicator output
pin, indicating when Vcc is less than Vbat.
DATA OUT
DATA IN
PLD INPUT
OUTPUT
OUTPUT
SELECT
MUX
PSD9XX Family
PORT D PIN
53