PSD935G2-90U STMicroelectronics, PSD935G2-90U Datasheet - Page 29

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PSD935G2-90U

Manufacturer Part Number
PSD935G2-90U
Description
Manufacturer
STMicroelectronics
Datasheet

Specifications of PSD935G2-90U

Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Package Type
TQFP
Mounting
Surface Mount
Pin Count
80
Lead Free Status / RoHS Status
Compliant

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The
PSD935G2
Functional
Blocks
(cont.)
28
PSD9XX Family
Figure 6. Priority Level of Memory and I/O Components
9.1.3.1. Memory Select Configuration for MCUs with Separate Program and Data Spaces
The 80C51 and compatible family of microcontrollers, can be configured to have separate
address spaces for code memory (selected using PSEN) and data memory (selected using
RD). Any of the memories within the PSD935G2 can reside in either space or both spaces.
This is controlled through manipulation of the VM register that resides in the PSD’s CSIOP
space.
The VM register is set using PSDsoft to have an initial value. It can subsequently be
changed by the microcontroller so that memory mapping can be changed on-the-fly.
For example, you may wish to have SRAM and main Flash in Data Space at boot, and
secondary Flash memory in Program Space at boot, and later swap main and secondary
Flash memory. This is easily done with the VM register by using PSDsoft to configure it for
boot up and having the microcontroller change it when desired.
Table 11 describes the VM Register.
NOTE: Bits 6-5 are not used.
Table 11. VM Register
Bit 7
PIO_EN
0 = disable
PIO mode
1= enable
PIO mode
Highest Priority
Lowest Priority
Bit 6* Bit 5*
*
*
*
*
FL_Data Boot_Data
0 = RD
can’t
access
Flash
1 = RD
access
Flash
Bit 4
0 = RD
can’t
access
Boot Flash Flash
1 = RD
access
Boot Flash Flash
Secondary Flash Memory
Bit 3
Main Flash Memory
SRAM, I/O
Level 1
Level 2
Level 3
0 = PSEN 0 = PSEN
can’t
access
1 = PSEN 1 = PSEN
access
FL_Code
Bit 2
Boot_Code SRAM_Code
can’t
access
Boot Flash
access
Boot Flash
PSD935G2
Bit 1
0 = PSEN
can’t
access
SRAM
1 = PSEN
access
SRAM
Bit 0

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