PSD935G2-90U STMicroelectronics, PSD935G2-90U Datasheet - Page 77

• Manufacturer Part Number: PSD935G2-90U
• Manufacturer: STMicroelectronics

Specifications of PSD935G2-90U

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: TQFP
• Mounting: Surface Mount
• Pin Count: 80
• Lead Free Status / RoHS Status: Compliant

Microcontroller Interface – PSD935G2 AC/DC Parameters
(3.0 V to 3.6 V Versions)
Write Timing
PLD Combinatorial Timing
PSD9XX Family
NOTE: 1. Fast Slew Rate output available on Port C and F.
76
NOTES: 1. Any input used to select an internal PSD935G2 function.
Symbol
t
t
Symbol
PD
ARD
t
t
t
t
t
t
t
t
t
t
t
t
LVLX
AVLX
LXAX
AVWL
SLWL
DVWH
WHDX
WLWH
WHAX1
WHAX2
WHPV
AVPV
2. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
3. WR timing has the same timing as E, DS signals.
4. t
WHAX2
PLD Input Pin/Feedback to
PLD Combinatorial Output
PLD Array Delay
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
Address Valid to Leading
Edge of WR
CS Valid to Leading Edge of WR
WR Data Setup Time
WR Data Hold Time
WR Pulse Width
Trailing Edge of WR to Address Invalid
Trailing Edge of WR to DPLD Address
Input Invalid
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
Address Input Valid to Address
Output Delay
is Address hold time for DPLD inputs that are used to generate chip selects for internal PSD memory.
(3.0 V to 3.6 V Versions)
Parameter
Parameter
(5 V ± 10%)
Conditions
(Notes 1 and 3)
(Notes 3 and 4)
Min
Conditions
(Note 1)
(Note 1)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 2)
-90
Max
38
23
Min
-12
Min
22
15
15
40
40
Max
7
8
5
8
0
43
27
-90
Max
PSD935G2
33
30
Add 20
TURBO
OFF
Min
24
10
18
18
45
45
10
9
8
0
-12
(Note 1)
Sub 6
Slew
Rate
Max
33
35
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns