PSD935G2-90U STMicroelectronics, PSD935G2-90U Datasheet - Page 31
PSD935G2-90U
Manufacturer Part Number
PSD935G2-90U
Description
Manufacturer
STMicroelectronics
Datasheet
1.PSD935G2-90U.pdf
(91 pages)
Specifications of PSD935G2-90U
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Package Type
TQFP
Mounting
Surface Mount
Pin Count
80
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PSD935G2-90U
Manufacturer:
STMicroelectronics
Quantity:
409
The
PSD935G2
Functional
Blocks
(cont.)
30
PSD9XX Family
9.1.4 Page Register
The eight bit Page Register increases the addressing capability of the microcontroller by a
factor of up to 256. The contents of the register can also be read by the microcontroller.
The outputs of the Page Register (PGR0-PGR7) are inputs to the PLD decoder and
can be included in the Flash Memory, secondary Flash memory, and SRAM chip select
equations.
If memory paging is not needed, or if not all 8 page register bits are needed for memory
paging, then these bits may be used in the PLD for general logic. See Application
Notes.
Figure 9 shows the Page Register. The eight flip flops in the register are connected to the
internal data bus D0-D7. The microcontroller can write to or read from the Page Register.
The Page Register can be accessed at address location CSIOP + E0h.
Figure 9. Page Register
RESET
D0 - D 7
R/W
D0
D1
D2
D3
D4
D5
D6
D7
REGISTER
PAGE
Q 0
Q 1
Q 2
Q 3
Q 4
Q 5
Q 6
Q 7
PGR0
PGR1
PGR2
PGR3
PGR4
PGR5
PGR6
PGR7
FLASH
DPLD
GPLD
AND
PLD
PSD935G2
INTERNAL
SELECTS
AND LOGIC