PSD935G2-90U STMicroelectronics, PSD935G2-90U Datasheet - Page 51

• Manufacturer Part Number: PSD935G2-90U
• Manufacturer: STMicroelectronics

Specifications of PSD935G2-90U

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: TQFP
• Mounting: Surface Mount
• Pin Count: 80
• Lead Free Status / RoHS Status: Compliant

50
PSD9XX Family
The
PSD935G2
Functional
Blocks
(cont.)
9.4.3.1 Control Register
Any bit set to ‘0’ in the Control Register sets the corresponding Port pin to MCU I/O Mode,
and a ‘1’ sets it to Address Out Mode. The default mode is MCU I/O. Only Ports E, F and
G have an associated Control Register.
9.4.3.2 Direction Register
The Direction Register controls the direction of data flow in the I/O Ports. Any bit set to ‘1’
in the Direction Register will cause the corresponding pin to be an output, and any bit set
to ‘0’ will cause it to be an input. The default mode for all port pins is input.
Figures 21 and 23 show the Port Architecture diagrams for Ports A/B/C and E/F/G
respectively. The direction of data flow for Ports A, B, C and F are controlled by the
direction register.
An example of a configuration for a port with the three least significant bits set to output
and the remainder set to input is shown in Table 21. Since Port D only contains four pins,
the Direction Register for Port D has only the four least significant bits active.
Table 19. Port Configuration Registers
*
9.4.3 Port Configuration Registers (PCRs)
Each port has a set of PCRs used for configuration. The contents of the registers can be
accessed by the microcontroller through normal read/write bus cycles at the addresses
given in Table 6. The addresses in Table 6 are the offsets in hex from the base of the
CSIOP register.
The pins of a port are individually configurable and each bit in the register controls its
respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three PCRs,
shown in Table 19, are used for setting the port configurations. The default power-up state
for each register in Table 22 is 00h.
Table 20. Port Pin Direction Control
Table 21. Port Direction Assignment Example
NOTE: See Table 22 for Drive Register bit definition.
Direction Register Bit
Register Name
Bit 7
Control
Direction
Drive Select*
0
0
1
Bit 6
0
E,F,G
A,B,C,D,E,F,G
A,B,C,D,E,F,G
Port
Bit 5
0
Port Pin Mode
Output
Input
Bit 4
0
MCU Access
Write/Read
Write/Read
Write/Read
Bit 3
0
Bit 2
1
PSD935G2
Bit 1
1
Bit 0
1