PSD935G2-90U STMicroelectronics, PSD935G2-90U Datasheet - Page 41

• Manufacturer Part Number: PSD935G2-90U
• Manufacturer: STMicroelectronics

Specifications of PSD935G2-90U

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: TQFP
• Mounting: Surface Mount
• Pin Count: 80
• Lead Free Status / RoHS Status: Compliant

The
PSD935G2
Functional
Blocks
(cont.)
40
PSD9XX Family
9.3.3.3 80C51XA
The Philips 80C51XA microcontroller family supports an 8- or 16-bit multiplexed bus that
can have burst cycles. Address bits A[3:0] are not multiplexed, while A[19:4] are
multiplexed with data bits D[15:0] in 16-bit mode. In 8-bit mode, A[11:4] are multiplexed
with data bits D[7:0].
The 80C51XA can be configured to operate in eight-bit data mode. (shown in Figure 18).
The 80C51XA improves bus throughput and performance by executing Burst cycles for
code fetches. In Burst Mode, address A19-4 are latched internally by the PSD935G2, while
the 80C51XA changes the A3-0 lines to fetch up to 16 bytes of code. The PSD access
time is then measured from address A3-A0 valid to data in valid. The PSD bus timing
requirement in Burst Mode is identical to the normal bus cycle, except the address setup
and hold time with respect to ALE does not apply.
9.3.3.4 68HC11
Figure 19 shows an interface to a 68HC11 where the PSD935G2 is configured in 8-bit
multiplexed mode with E and R/W settings. The DPLD can generate the READ and WR
signals for external devices.
Table 15. 80C251 Configurations
Configuration
1
2
3
4
Read/Write
WR
RD
PSEN
WR
PSEN only
WR
PSEN only
WR
RD
PSEN
80C251
Pins
Connecting to
PSD935G2
CNTL0
CNTL1
CNTL2
CNTL0
CNTL1
CNTL0
CNTL1
CNTL0
CNTL1
CNTL2
Pins
Non-Page Mode, 80C31 compatible
A
Non-Page Mode
A
Page Mode
A
Page Mode
A
[
[
[
[
7:0
7:0
15:8
15:8
]
]
]
]
multiplex with D
multiplex with D
multiplex with D
multiplex with D
PSD935G2
Page Mode
[
[
7:0
7:0
[
[
7:0
7:0
}
}
}
}