PSD935G2-90U STMicroelectronics, PSD935G2-90U Datasheet - Page 57

• Manufacturer Part Number: PSD935G2-90U
• Manufacturer: STMicroelectronics

Specifications of PSD935G2-90U

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: TQFP
• Mounting: Surface Mount
• Pin Count: 80
• Lead Free Status / RoHS Status: Compliant

The
PSD935G2
Functional
Blocks
(cont.)
56
PSD9XX Family
NOTES: 1. Power Down does not affect the operation of the PLD. The PLD operation in this
Table 24. Power Down Mode’s Effect on
Table 25. PSD935G2 Timing and Standby Current During Power
9.5.1 Automatic Power Down (APD) Unit and Power Down Mode (cont.)
Power Down Mode
By default, if you enable the PSD APD unit, Power Down Mode is automatically enabled.
The device will enter Power Down Mode if the address strobe (ALE/AS) remains inactive
for fifteen CLKIN (pin PD1) clock periods.
The following should be kept in mind when the PSD is in Power Down Mode:
Power Down
•
•
•
•
•
Port Function
If the address strobe starts pulsing again, the PSD will return to normal operation.
The PSD will also return to normal operation if either the CSI input returns low or the
Reset input returns high.
The MCU address/data bus is blocked from all memories and PLDs.
Various signals can be blocked (prior to Power Down Mode) from entering the PLDs
by setting the appropriate bits in the PMMR registers. The blocked signals include
MCU control signals and the common clock (CLKIN). Note that blocking CLKIN from
the PLDs will not block CLKIN from the APD unit.
All PSD memories enter Standby Mode and are drawing standby current. However,
the PLDs and I/O ports do not go into Standby Mode because you don’t want to
have to wait for the logic and I/O to “wake-up” before their outputs can change. See
Table 24 for Power Down Mode effects on PSD ports.
Typical standby current is 50 µA for 5 V parts. This standby current value assumes
that there are no transitions on any PLD input.
Mode
MCU I/O
PLD Out
Address Out
Data Port
Peripheral I/O
2. Typical current consumption assuming no PLD inputs are changing state and
mode is based only on the Turbo Bit.
the PLD Turbo bit is off.
Ports
Down Mode
Propagation
Normal tpd
(Note 1)
Delay
PLD
No Change
No Change
Undefined
Three-State
Three-State
Pin Level
No Access
Memory
Access
Time
Recovery Time
to Normal
Access
Access
tLVDV
Standby
(Note 2)
5V V
Current
Typical
50 µA
PSD935G2
CC
,