PSD935G2-90U STMicroelectronics, PSD935G2-90U Datasheet - Page 61

• Manufacturer Part Number: PSD935G2-90U
• Manufacturer: STMicroelectronics

Specifications of PSD935G2-90U

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: TQFP
• Mounting: Surface Mount
• Pin Count: 80
• Lead Free Status / RoHS Status: Compliant

The
PSD935G2
Functional
Blocks
(cont.)
60
PSD9XX Family
9.5.3 Reset and Power On Requirement
9.5.3.1 Power On Reset
Upon power up the PSD935G2 requires a reset pulse of tNLNH-PO (minimum 1 ms) after
V
some of the registers and sets the Flash into operating mode. After the rising edge of
reset, the PSD935G2 remains in the reset state for an additional tOPR (maximum 120 ns)
nanoseconds before the first memory access is allowed.
The PSD935G2 Flash memory is reset to the read array mode upon power up. The FSi
and CSBOOTi select signals along with the write strobe signal must be in the false
state during power-up reset for maximum security of the data contents and to remove
the possibility of data being written on the first edge of a write strobe signal. Any Flash
memory write cycle initiation is prevented automatically when V
9.5.3.2 Warm Reset
Once the device is up and running, the device can be reset with a much shorter pulse of
tNLNH (minimum 150 ns). The same tOPR time is needed before the device is operational
after warm reset. Figure 26 shows the timing of the power on and warm reset.
9.5.3.3
Table 28 shows the I/O pin, register and PLD status during power on reset, warm reset
and power down mode. PLD outputs are always valid during warm reset, and they are
valid in power on reset once the internal PSD configuration bits are loaded. This loading of
PSD is completed typically long before the V
is active, the state of the outputs are determined by the equations specified in PSDsoft.
Figure 26. Power On and Warm Reset Timing
CC
V
RESET
CC
is steady. During this time period the device loads internal configurations, clears
OPERATING LEVEL
I/O Pin, Register and PLD Status at Reset
POWER ON RESET
t NLNH – PO
CC
ramps up to operating level. Once the PLD
t OPR
CC
PSD935G2
is below VLKO.
t NLNH
t NLNH-A
WARM
RESET
t OPR