ST7LIT10BF1 STMicroelectronics, ST7LIT10BF1 Datasheet - Page 76

• Manufacturer Part Number: ST7LIT10BF1
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7LIT10BF1

• Up To 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• Clock Sources: Internal 1% RC oscillator (on ST7FLITE15B and ST7FLITE19B), crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Auto Wake-up from Halt, Wait and Slow

ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
Bit 1= TRAN2 Transfer enable2
This bit is read/write by software, cleared by hard-
ware after each completed transfer and set by
hardware after reset. It controls the transfers on
CNTR2.
It allows the value of the Preload DCRx registers
to be transferred to the Active DCRx registers after
the next overflow event.
The OPx bits are transferred to the shadow OPx
bits in the same way.
Notes:
1. DCR2/3 transfer will be controlled using this bit
if ENCNTR2 bit is set.
2. This bit must not be reset by software
Bit 0 = TRAN1 Transfer enable 1
This bit is read/write by software, cleared by hard-
ware after each completed transfer and set by
hardware after reset. It controls the transfers on
CNTR1. It allows the value of the Preload DCRx
registers to be transferred to the Active DCRx reg-
isters after the next overflow event.
The OPx bits are transferred to the shadow OPx
bits in the same way.
Notes:
1. DCR0,1 transfers are always controlled using
this bit.
2. DCR2/3 transfer will be controlled using this bit
if ENCNTR2 is reset.
3.This bit must not be reset by software
AUTORELOAD REGISTER2 (ATR2H)
Read / Write
Reset Value: 0000 0000 (00h)
76/159
1
15
0
0
0
0
ATR11 ATR10 ATR9
ATR8
8
AUTORELOAD REGISTER (ATR2L)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 11:0 = ATR2[11:0] Autoreload Register 2.
This is a 12-bit register which is written by soft-
ware. The ATR2 register value is automatically
loaded into the upcounter CNTR2 when an over-
flow of CNTR2 occurs. The register value is used
to
ENCNTR2 is set.
DEAD TIME GENERATOR REGISTER (DTGR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = DTE Dead Time Enable
This bit is read/write by software. It enables a dead
time generation on PWM0/PWM1.
0: No Dead time insertion.
1: Dead time insertion enabled.
Bits 6:0 = DT[6:0] Dead Time Value
These bits are read/write by software. They define
the dead time inserted between PWM0/PWM1.
Dead time is calculated as follows:
Dead Time = DT[6:0] x Tcounter1
Note:
1. If DTE is set and DT[6:0]=0, PWM output sig-
nals will be at their reset state.
ATR7
DTE
7
7
set
ATR6
DT6
the
ATR5
DT5
PWM2/PWM3
ATR4
DT4
ATR3
DT3
frequency
ATR2
DT2
ATR1
DT1
when
ATR0
DT0
0
0