IRCC2.0 SMSC Corporation, IRCC2.0 Datasheet - Page 23

• Manufacturer Part Number: IRCC2.0
• Description: Infrared Communications Controller
• Manufacturer: SMSC Corporation

The IrCC 2.0 is partially enabled through binary
controls found in two 8-byte register banks. The
banks, the ACE550 UART Controls and the SCE
Controls, are selected with the nACE and nSCE
register-bank selector inputs found in the
Interface Description.
If nACE is zero, the three least significant bits of
the Host Address Bus decode the 16C550A
SCE CONTROLS
The IrCC 2.0 SCE Registers are arranged in 7-
byte blocks.
blocks, six are used in this implementation.
BLOCK
X
0
0
0
0
DLAB
Of the eight possible register
X
X
X
X
X
X
X
0
0
0
1
1
ADDRESS
A2
7
0
1
2
3
0
0
0
0
0
0
1
1
1
1
0
0
Table 12 - 16C550A UART Addressing
A1
Table 13 - SCE Register Addressing
0
0
0
1
1
1
0
0
1
1
0
0
DIRECTION
A0
0
0
1
0
0
1
0
1
0
1
0
1
R/W
R/W
R/W
RO
RO
REGISTERS
DIRECTION
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read
Write
Read
Write
23
UART control registers.
SCE control bank is addressed. All of the IrCC
2.0 registers are 8 bits wide.
ACE UART CONTROLS
The table below (Table 12) lists the ACE UART
Control Registers.
16C550A
description.
The Master Block Control Register controls
access to the register blocks. Table 13 lists all of
the SCE registers in all blocks.
Interrupt Identification
Master Block Control
Interrupt Identification
REGISTER NAME
Line Status (read)
REGISTER NAME
Interrupt Enable
Interrupt Enable
Transmit Buffer
Modem Control
Data Register
implementation
Receive Buffer
Modem Status
Divisor (MSB)
Divisor (LSB)
FIFO Control
Line Control
Line Status
Scratchpad
See the current SMSC
If nSCE is zero, the
for
a
complete