IRCC2.0 SMSC Corporation, IRCC2.0 Datasheet - Page 31

• Manufacturer Part Number: IRCC2.0
• Description: Infrared Communications Controller
• Manufacturer: SMSC Corporation

Bus Status Register (Address 6)
FIFO Indicators (read-only)
The FIFO Indicators reflect the current status of
the SCE FIFO.
FIFO Not Empty, bit 7
The FIFO Not Empty bit when set to one
indicates that there is data in the SCE FIFO.
FIFO Full, bit 6
The FIFO Full bit when set to one indicates that
there is no room for data in the SCE FIFO.
Time-Out, bit 5
The Time-Out bit is the IOCHRDY time-out error
bit. The Time-Out bit when set to one indicates
that an IOCHRDY time-out error has occurred
(see the IOCHRDY Time-Out section on page
79). Time-Out is reset by the IrCC 2.0 System
Reset, following a read of the Bus Status
register, and following a Master Reset.
Memory Count, bits 1-4
Memory Count indicates the status of received
IrDA messages in memory. Memory Count is
31
incremented whenever the first byte of a
message is read from the SCE FIFO.
example, if Memory Count=3, there are currently
two complete messages in memory.
Memory counts are 0-8; i.e., there can be a
maximum of eight contiguous received IrDA
messages. Memory Count is only valid during
receive. Memory Count is reset to zero during
POR, Master Reset, and Error Reset (see the
Master Block Control register). Note: Memory
Count is closely related to the Message Count in
SCE Line Control Register B. Memory Count will
typically
depending on the size of the received messages
and the speed of the host bus interface.
Valid Frame, bit 0
The Valid Frame bit reflects the state of the
internal state variable nActive Frame.
nActive Frame=0 (active) Valid Frame=1 (active).
When nActive Frame=1 (inactive) Valid Frame=0
(inactive). Valid Frame is only defined for the
SCE
Encoder/Decoders during Transmit and Receive.
IrDA
fall
behind
FIR
and
the
Message
Consumer
Count
When
Legal
For
IR