IRCC2.0 SMSC Corporation, IRCC2.0 Datasheet - Page 71

• Manufacturer Part Number: IRCC2.0
• Description: Infrared Communications Controller
• Manufacturer: SMSC Corporation

The Bus Interface I/O block contains a 128-byte
FIFO, DMA/Interrupt logic, and multiplexers to
control access to the FIFO and the ISA Bus
(Figure 36).
FIFO MULTIPLEXER
SCE FIFO Access
The FIFO Multiplexer controls the configuration
of the SCE FIFO in the Bus Interface I/O Block.
This configuration can be inferred from the state
of the SCE Modes bits in Line Control Register
B.
disabled, or the transmit mode is enabled, the
FIFO is configured for transmit, otherwise, the
FIFO is configured for receive.
Transmit in Figure 36, above, can be satisfied by
the inverse of the SCE Modes msb; e.g., nD7.
HOST FIFO Access
When
16550A UART
Databus Multiplexer
Loopback
Transmit
the
transmit/receive
I/O & Interrupt
ISA Bus
Multiplexer
Control
SCE
FIFO
FIGURE 36 - BUS INTERFACE I/O BLOCK
modes
The signal
BUS INTERFACE I/O
are
Loopback
128-byte
71
FIFO
0
0
1
The Databus Multiplexer provides exclusive ISA
Bus access to either the 16C550A UART or the
IrCC 2.0 SCE depending on the state of Block
Control bits. Disabled blocks are disconnected
from the ISA Bus.
The host always has read access to the FIFO,
regardless of the state of the SCE Modes bits, or
the Loopback bit. The host has write access to
the FIFO when the Loopback bit is inactive and
the transmit/receive modes are disabled or the
Transmit mode is enabled.
128-BYTE SCE FIFO
FIFO Timing & Controls
The FIFO requires interleaved access timing to
allow simultaneous FIFO data reads and data
Transmit
X
0
1
Function
FIFO In to SCE Rx
FIFO Out to Host Bus
FIFO In to Host Bus
FIFO Out to SCE Tx
FIFO In to SCE Rx
FIFO Out to SCE Tx