IRCC2.0 SMSC Corporation, IRCC2.0 Datasheet - Page 6

• Manufacturer Part Number: IRCC2.0
• Description: Infrared Communications Controller
• Manufacturer: SMSC Corporation

DMAEN
DMAEN is used by the chip-level interface to
tristate the IrCC 2.0 DRQ output when the DMA
Enable bit is inactive. The DMA Enable bit is
located in SCE Configuration Register B, bit 0.
IRQEN
IRQEN is used by the chip-level interface to
tristate the IrCC 2.0 IRQ output when the OUT2
bit is inactive.
16C550A MODEM Control Register.
Power Down
The Power Down pin is used by the chip-level
interface to put the SCE into low power mode.
Note: Power Down only forces the SCE into low
power mode. The ACE power down function is
not a part of this specification.
Power Down
DMAEN
RESET
IRQEN
NAME
nACE
nSCE
GND
VCC
CLK
The OUT2 bit is located in
SIZE (BITS)
1
1
1
1
1
1
1
Table 6 - SYSTEM Signals
Output
Output
Power
Power
TYPE
Input
Input
Input
Input
Input
6
CHIP-LEVEL CONFIGURATION CONTROLS
The following signals come from chip-level
configuration registers. There are two types of
Chip-Level Configuration Controls: IrCC 2.0 -
Specific controls, and Legacy Controls.
types have equivalent controls in either the IrCC
2.0 ACE or SCE Registers.
The IrCC 2.0-Specific controls have been newly
added primarily to support the IrCC 2.0 block.
Provisions have been made in new chip-level
configuration contexts to accommodate these
signals.
The Legacy controls already exist in other
contexts. Provisions have been made in legacy
devices to accommodate these controls from
either the Chip-Level Configuration Registers or
the IrCC 2.0 Registers; i.e., the last updated
value from either source determines the current
control state and is visible in both registers.
System Clock
IrCC 2.0 System Reset
Low Power Control
DRQ Tristate Control
IRQ Tristate Control
ACE 550 Register Bank Select
SCE Register Bank Select
System Supply
System Ground
DESCRIPTION
Both