IRCC2.0 SMSC Corporation, IRCC2.0 Datasheet - Page 84

• Manufacturer Part Number: IRCC2.0
• Description: Infrared Communications Controller
• Manufacturer: SMSC Corporation

IrCC 2.0 Register addressing is controlled at the
chip level. Both the ACE bank select, nACE, and
the SCE bank select, nSCE, are decoded at the
chip level from the host address bus to access
HEX ADDRESS
000 - 3FF
410 - 4FF
400 - 407
408 - 40F
Address Bus
FIGURE 53 - CHIP-LEVEL IrCC 2.0 ADDRESS DECODE
CHIP-LEVEL IrCC 2.0 ADDRESSING SUPPORT
I/O Select
AEN
Table 36 - IrCC 2.0 Address Decode at '400'hex
Chip-Level
nACE
Decoder
Address
1
0
1
1
nSCE
1
1
0
1
84
Select
Select
data in the IrCC 2.0 register banks (Figure 53).
Table 36 illustrates a chip-level IrCC 2.0 address
decoder using a base address of ‘400’hex.
ACE
SCE
IrCC 2.0 registers not accessible
ACE UART registers enabled
SCE registers enabled
IrCC 2.0 registers not accessible
nACE
nSCE
DESCRIPTION
IrCC