IRCC2.0 SMSC Corporation, IRCC2.0 Datasheet - Page 39

• Manufacturer Part Number: IRCC2.0
• Description: Infrared Communications Controller
• Manufacturer: SMSC Corporation

REGISTER BLOCK THREE
Register Block Three contains the IrCC 2.0 Block
Identifier Registers.
classify the hardware Manufacturer, the Device
ID, the Version number, and Host interface
Note 1: The default values for these registers assume the values that have been programmed in chip-
level configuration registers.
SMSC ID (Addresses 0 - 1)
The SMSC ID registers contain a 16 bit
manufacturer identification code. Address zero
contains the high byte of this code, address one
contains the low byte.
Chip ID (Address 2)
The Chip ID register specifically identifies this
SMSC product.
Version Number (Address 3)
The Version Number register identifies the
revision-level of the product referenced by the
Chip ID register.
IRQ Level/ DMA Channel (Address 4)
IRQ Level, bits 4 - 7
The IRQ Level bits identify the current active IRQ
number for this device.
A2
0
0
0
0
1
1
1
Address
A1
0
0
1
1
0
0
1
A0
0
1
0
1
0
1
0
Direction
RO
RO
RO
RO
RO
RO
RO
These read-only registers
The value comes
D7
Table 27 - Register Block Three
D6
IRQ Level
D5
39
SMSC ID (high-byte)
SMSC ID (low-byte)
VERSION Number
Software Select A
Software Select B
parameters. Bits and registers marked “reserved”
in the table below cannot be written and return 0x
when read. Programmers must set reserved bits
to 0 when writing to registers that contain
reserved bits.
from the 4 bit IRQ Level Bus found in the
Interface Description.
DMA Channel, bits 0 - 3
The DMA Channel bits identify the current active
DMA Channel number for this device. The value
comes from the 4 bit DMA Channel Bus found in
the Interface Description.
Software Select A (Address 5)
The Software Select A register is software-only
controlled from a chip-level configuration register
(see the IrCC 2.0-Specific Chip-Level Controls
section on page 7).
Software Select B (Address 6)
The Software Select B register is software-only
controlled from a chip-level configuration register
(see the IrCC 2.0-Specific Chip-Level Controls
section on page 7).
Description
D4
CHIP ID
D3
DMA Channel
D2
D1
D0
Default
'10'hex
'B8'hex
'F2'hex
'00'hex
Note 1
Note 1
Note 1