IRCC2.0 SMSC Corporation, IRCC2.0 Datasheet - Page 42

• Manufacturer Part Number: IRCC2.0
• Description: Infrared Communications Controller
• Manufacturer: SMSC Corporation

REGISTER BLOCK FIVE
Register Block Five contains the Automatic
Transceiver Controls, IR Half Duplex Timeout,
and Transmit Delay Timer.
Note 1: The default value for the IR Half Duplex Timeout assumes the value that has been
programmed in the chip-level configuration register (see the IR Half Duplex Timeout Register (Address
1) section).
ATC Register (Address 0)
See the Automatic Transceiver Control section
on page 69.
ATC nProg/Ready, bit 7
The
programming
programming completion status (see Figure 34 -
ATC Programming). When ATC nProg/Ready =
0 (default), an ATC programming cycle is in
progress; when ATC nProg/Ready = 1, ATC
programming is complete. Note: This bit is self-
setting.
programming cycle by setting this bit low, the
hardware automatically sets this bit high when
the programming cycle has ended.
A2
0
0
0
0
1
1
1
Address
ATC
A1
0
0
1
1
0
0
1
When a user initiates an ATC
A0
0
1
0
1
0
1
0
nProg/Ready
cycles
Direction
R/W
R/W
R/W
and
bit
nProg/
Ready
rsrvd
ATC
indicates
D7
Table 29 - SCE Register Block Five
initiates
Speed
ATC
DT6
D6
ATC
ATC
Enabl
SCE Transmit Delay Timer
ATC
42
DT5
D5
IR Half Duplex Timeout
e
ATC Speed, bit 6
The ATC Speed bit determines the IBM/Temic
transceiver speed setting. When ATC Speed = 0
(default), low speed mode (up to 1.152 Mbps) is
selected; when ATC Speed = 1, high speed
mode (4 Mbps) is selected.
ATC Enable, bit 5
The
Transceiver Control. When ATC Enable = 0
(default),
disabled; when ATC Enable = 1, Automatic
Transceiver Control is enabled.
IR Half Duplex Timeout Register (Address 1)
The IR Half Duplex Timeout declares the
minimum link turnaround delay time. This means
that when the infrared channel changes direction
the interval programmed in the IR Half Duplex
Timeout
transmitter
regardless of the state of the individual Tx or Rx
enables.
ATC Register
Bits and registers marked reserved in the table
below cannot be written and return 0s when
read. Programmers must set reserved bits to 0
when writing to registers that contain reserved
bits.
Description
reserved
reserved
reserved
reserved
DT4
D4
ATC
register
Automatic
The IR Half Duplex Timeout is
DT3
or
D3
Enable
reserved
receiver
DT2
must
D2
bit
Transceiver
DT1
elapse
D1
can
enables
DT0
be
D0
before
Control
Automatic
activated,
Default
'80'hex
'03'hex
Note
the
1
is
Field Code Changed