IRCC2.0 SMSC Corporation, IRCC2.0 Datasheet - Page 33

• Manufacturer Part Number: IRCC2.0
• Description: Infrared Communications Controller
• Manufacturer: SMSC Corporation

Half Duplex, bit 2
When Half Duplex is zero (default), the 16C550A
is in full duplex mode. The Half Duplex bit only
supports the 16C550A UART; i.e., this bit has no
effect on the IrCC 2.0 SCE. The Half Duplex bit
is analogous to the chip-level configuration
register Half Duplex bit and has the same effect
on the UART. Provisions have been made in
legacy devices to accommodate Half Duplex
selection
configuration registers or the IrCC 2.0 Half
Duplex bit; i.e., the last write from either source
determines the current mode selection and is
visible in both registers.
Tx/Rx Polarity Bits, 0 - 1
The Tx and Rx Polarity bits define the active
states for signals entering and exiting the Output
Multiplexer ports. Internal IrCC 2.0 Active states
are typically decoded as zero. The Tx Polarity bit
default is one; the Rx Polarity bit default is zero.
D6
0
0
0
0
0
0
0
0
1
through
D5
X
0
0
0
0
1
1
1
1
either
D4
X
0
0
1
1
0
0
1
1
SIGNAL
0
0
1
1
Table 19 - IrCC 2.0 Logical Block Controls
D3
0
1
0
1
0
1
1
X
0
the
Table 20 - Tx/Rx Polarity Bit Effects
POLARITY BIT
COM
IrDA SIR - A
ASK IR
IrDA SIR - B
IrDA HDLC
IrDA4PPM
CONSUMER
RAW IR
OTHER
chip-level
MODE
0
1
0
1
33
16C550A UART COM Port (default)
Up to 115.2 Kbps, Variable 3/16 Pulse
Amplitude Shift Keyed Ir Interface
Up to 115.2 Kbps, Fixed 1.6Fs Pulse
Includes 0.576 Mbps & 1.152 Mbps
Includes 4 Mbps
TV Remote
Direct IR Diode Control
Reserved
For backward compatibility, the Tx and Rx
Polarity bits do not apply to COM mode; i.e.,
when the Block Control bits are zero.
relationship between the Output Multiplexer port
signals and the Polarity bits is an exclusive-or
(Table 20). For example, if the IRRx pin in the
Output Multiplexer is one and the Rx Polarity bit
is zero, the signal is inactive and therefore
decoded as a one. The IrCC 2.0 Tx Polarity bit
(bit 1) is equivalent to the Transmit Polarity bit in
the chip-level configuration space of earlier
devices;
Register, Serial Port 2, Logical Device 5,
Register 0xF1.
equivalent to the Receive Polarity bit in the same
register. Provisions have been made in legacy
devices to accommodate Polarity bit selection
through
registers or the SCE registers; i.e., the last write
from either source determines the current
Polarity bit value and is visible in both registers.
DECODED SIGNAL
either
e.g.,
DESCRIPTION
0
1
1
0
the
The Rx Polarity bit (bit 0) is
the
FDC37C93x
chip-level
configuration
IR
Option
The