mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1051

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

42.4.9 DMA Support
If the DMAEN bit is cleared and the IICIE bit is set, an interrupt condition generates an
interrupt request. If the DMAEN bit is set and the IICIE bit is set, an interrupt condition
generates a DMA request instead. DMA requests are generated by the transfer complete
flag (TCF).
If the DMAEN bit is set, the only arbitration lost is to another I2C module (error), and
SCL low timeouts (error) generate CPU interrupts. All other events initiate a DMA
transfer.
42.5 Initialization/Application Information
Module Initialization (Slave)
Module Initialization (Master)
Freescale Semiconductor, Inc.
1. Write: Control Register 2
2. Write: Address Register 1 to set the slave address
3. Write: Control Register 1 to enable the I2C module and interrupts
4. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data
5. Initialize RAM variables used to achieve the routine shown in the following figure
• to enable or disable general call
• to select 10-bit or 7-bit addressing mode
After the system recovers and is in run mode, restart the I2C
module if necessary. The SCL line is not held low until the I2C
module resets after address matching.
Before the last byte of master receive mode, TXAK must be set
to send a NACK after the last byte’s transfer. Therefore, the
DMA must be disabled before the last byte’s transfer.
In 10-bit address mode transmission, the addresses to send
occupy 2-3 bytes. During this transfer period, the DMA must be
disabled because the C1 register is written to send a repeat start
or to change the transfer direction.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
NOTE
NOTE
NOTE
Chapter 42 Inter-Integrated Circuit (I2C)
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