mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 90

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

System modules
1. Requires the peripheral and the peripheral interrupt to be enabled. The internal module's WUME bit enables the internal
3.4.5.2 LLWU register reset
All LLWU registers are reset by Chip Reset not VLLS and by other reset types that
trigger Chip Reset not VLLS. LLWU registers are unaffected by reset types that do not
trigger Chip Reset not VLLS. For more information about the types of reset available on
this chip, refer to the
3.4.6 Computer Operating Properly (COP) Watchdog
This section summarizes how the module has been configured in the chip.
3.4.6.1 COP clocks
The two clock inputs for the COP are the 1 kHz clock and the bus clock.
3.4.6.2 COP watchdog operation
The COP watchdog is intended to force a system reset when the application software fails
to execute as expected. To prevent a system reset from the COP timer (when it is
enabled), application software must reset the COP counter periodically. If the application
program gets lost and fails to reset the COP counter before it times out, a system reset is
generated to force the system back to a known starting point.
After any reset, the COP watchdog is enabled. If the COP watchdog is not used in an
application, it can be disabled by clearing COPC[COPT] in the SIM.
90
Power management
Programming model
module flag as a wakeup input. After wakeup, the flags are cleared based on the peripheral clearing mechanism.
Clocking
Topic
Configuration
Table 3-14. Reference links to related information
System Integration
Related module
Reset
Module (SIM)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
details.
Preliminary
Power management
Clock distribution
Reference
SIM
Freescale Semiconductor, Inc.