mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 919

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

38.3.5 SPI data register high (SPIx_DH)
Refer to the description of the DL register.
Addresses: SPI0_DH is FFFF_81A0h base + 4h offset = FFFF_81A4h, SPI1_DH is FFFF_81B0h base + 4h offset = FFFF_81B4h
38.3.6 SPI data register low (SPIx_DL)
This register, together with the DH register, is both the input and output register for SPI
data. A write to the registers writes to the transmit data buffer, allowing data to be queued
and transmitted.
When the SPI is configured as a master, data queued in the transmit data buffer is
transmitted immediately after the previous transmission has completed.
The SPTEF bit in the S register indicates when the transmit data buffer is ready to accept
new data. When the transmit DMA request is disabled (TXDMAE is 0), the S register
must be read when SPTEF is set before writing to the SPI data registers; otherwise, the
write is ignored. When the transmit DMA request is enabled (TXDMAE is 1) when
SPTEF is set, the SPI data registers can be written automatically by DMA without
reading the S register first.
Data may be read from the SPI data registers any time after SPRF is set and before
another transfer is finished. Failure to read the data out of the receive data buffer before a
new transfer ends causes a receive overrun condition, and the data from the new transfer
is lost. The new data is lost because the receive buffer still held the previous character
and was not ready to accept the new data. There is no indication for a receive overrun
condition, so the application system designer must ensure that previous data has been
read from the receive buffer before a new transfer is initiated.
In 8-bit mode, only the DL register is available. Reads of the DH register return all zeros.
Writes to the DH register are ignored.
Freescale Semiconductor, Inc.
Bits[15:8]
Reset
Field
Read
7–0
Write
Bit
Data (high byte)
7
0
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
SPI0_DH field descriptions
0
5
Preliminary
0
4
Bits[15:8]
Description
0
3
Chapter 38 Serial Peripheral Interface (SPI)
0
2
0
1
0
0
919