mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 160

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Reset memory map and register descriptions
160
WAKEUP
WDOG
ILOP
ILAD
Field
LOC
LVD
PIN
6
5
4
3
2
1
0
Indicates a reset was caused by the power-on detection logic. Because the internal supply voltage was
ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred
while the internal supply was below the LVD threshold.
0
1
External reset pin
Indicates a reset was caused by an active-low level on the external RESETpin.
0
1
Watchdog
Indicates a reset was caused by the Computer Operating Properly (COP) watchdog timer timing out. This
reset source can be blocked by disabling the COP watchdog: write 00 to the SIM's COPC[COPT] field..
0
1
Illegal opcode
Indicates a reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
instruction is considered illegal if stop is disabled by ((SOPT4[STOPE] = 0) && (SOPT4[WAITE] = 0)) in
the SIM. The HALT instruction is considered illegal if the BDM interface is disabled by XCSR[ENBDM] =
0.
0
1
Illegal address
Indicates a reset was caused by an attempt to access an illegal address in the memory map.
0
1
Loss-of-clock reset
Indicates a reset was caused by a loss of external clock. The MCG clock monitor must be enabled for a
loss of clock to be detected. Refer to the detailed MCG description for information on enabling the clock
monitor.
0
1
Low-voltage detect reset
If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset occurs. This bit is
also set by POR.
0
1
Low leakage wakeup reset
Reset not caused by POR
Reset caused by POR
Reset not caused by external reset pin
Reset caused by external reset pin
Reset not caused by watchdog timeout
Reset caused by watchdog timeout
Reset not caused by an illegal opcode
Reset caused by an illegal opcode
Reset not caused by an illegal access
Reset caused by an illegal access
Reset not caused by a loss of external clock.
Reset caused by a loss of external clock.
Reset not caused by LVD trip or POR
Reset caused by LVD trip or POR
RCM_SRS0 field descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Table continues on the next page...
Preliminary
Description
Freescale Semiconductor, Inc.