mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 382

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Modes of Operation
Depending on the needs of the user application, a variety of stop modes are available that
allow the state retention, partial power down or full power down of certain logic and/or
memory. I/O states are held in all modes of operation. Several registers are used to
configure the various modes of operation for the device.
The following table describes the power modes available for the device.
1. See the devices Chip Configuration details for the size and location of the system RAM partitions.
382
RUN
WAIT
STOP
VLPR
VLPW
VLPS
LLS
VLLS3
VLLS2
VLLS1
Mode
MCU can be run at full speed and the internal supply is fully regulated (run regulation mode). This
mode is also referred to as normal run mode.
The CPU clock is gated off. The System Clock continues to operate; Bus Clocks, if enabled,
continue to operate; and run regulation is maintained.
The Core Clock is gated off. System Clock to other masters and Bus Clocks are stopped after all
stop acknowledge signals from supporting peripherals are valid.
The Core, System, Bus, and Flash Clock maximum frequencies are restricted in this mode. See the
Power Management chapter for details about the maximum allowable frequencies.
The Core Clock is gated off. The System, Bus, and Flash Clocks continue to operate, although their
maximum frequency is restricted. See the Power Management chapter for details on what the
maximum allowable frequencies are.
The Core Clock to the CPU is gated off. System clock to other masters and Bus Clocks are stopped
after all stop acknowledge signals from supporting peripherals are valid.
The CPU clocks are gated off. System clock and Bus Clocks are stopped after all stop
acknowledge signals from supporting peripherals are valid. MCU is placed in a low leakage mode
by reducing the voltage to internal logic. Internal logic states are retained.
The CPU clocks are gated off. System clock to other masters and Bus Clocks are stopped after all
stop acknowledge signals from supporting peripherals are valid. MCU is placed in a low leakage
mode by powering down the internal logic. All system RAM contents are retained and I/O states
held. FlexRAM contents are not retained. Internal logic states are not retained.
The CPU clocks are gated off. System clock to other masters and Bus Clocks are stopped after all
stop acknowledge signals from supporting peripherals are valid. MCU is placed in a low leakage
mode by powering down the internal logic and the system RAM3 partition. The system RAM2
partition can be optionally retained using the VLLSCTRL[RAM2PO] bit while the system RAM1
partition contents are always retained in this mode. FlexRAM contents are not retained. Internal
logic states are not retained.
The CPU clocks are gated off. System clock to other masters and Bus Clocks are stopped after all
stop acknowledge signals from supporting peripherals are valid. MCU is placed in a low leakage
mode by powering down the internal logic and all system RAM. A 32-byte register file (available in
all modes) contents are retained and I/O states held. FlexRAM contents are not retained. Internal
logic states are not retained.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Table 17-1. Power modes
1
Preliminary
Description
Freescale Semiconductor, Inc.