mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 327

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mcf51jf128

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mcf51jf128
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Mcf51jf128 Reference Manual
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Freescale Semiconductor, Inc
Datasheet

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Chapter 14 Crossbar Switch
When a slave bus is being IDLEd by the crossbar it remains parked with the last master
to use the slave port . This is done in an attempt to save the initial clock of arbitration
delay that otherwise would be seen if the master had to arbitrate to gain control of the
slave port.
14.3.2 Arbitration
The crossbar switch supports two arbitration schemes: a simple fixed-priority comparison
algorithm and a simple round-robin fairness algorithm.
The crossbar arbitration scheme is controlled by CPUCR[CBRR] bit in the processor's
CPU Configuration Register (CPUCR). See
CPU Configuration Register (CPUCR)
for
details. At reset, fixed-priority arbitration is enabled.
14.3.2.1 Arbitration During Undefined Length Bursts
All lengths of burst accesses lock out arbitration until the last beat of the burst.
14.3.2.2 Fixed-Priority Operation
When operating in fixed-priority mode, each master is assigned a unique priority level
with the highest numbered master having the highest priority (master 1 has lower priority
than master 3). If two masters request access to a slave port, the master with the highest
priority gains control over the slave port.
When a master makes a request to a slave port, the slave port checks if the new
requesting master's priority level is higher than that of the master that currently has
control over the slave port (unless the slave port is in a parked state). The slave port
performs an arbitration check at every clock edge to ensure that the proper master (if any)
has control of the slave port.
If the new requesting master's priority level is higher than that of the master that currently
has control of the slave port, the new requesting master is granted control over the slave
port at the next clock edge. The exception to this rule is if the master that currently has
control over the slave port is running a fixed length burst transfer or a locked transfer. In
this case, the new requesting master must wait until the end of the burst transfer or locked
transfer before it is granted control of the slave port.
If the new requesting master's priority level is lower than the master that currently has
control of the slave port, the new requesting master is forced to wait until the current
master runs one of the following cycles:
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Freescale Semiconductor, Inc.
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