mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 413

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mcf51jf128

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mcf51jf128
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Mcf51jf128 Reference Manual
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Freescale Semiconductor, Inc
Datasheet

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19.2 DMA Transfer Overview
The DMA module can move data within system memory (including memory and
peripheral devices) with minimal processor intervention, greatly improving overall
system performance. The DMA module consists of four independent, functionally
equivalent channels, so references to DMA in this chapter apply to any of the channels. It
is not possible to address all four channels at once.
The processor generates DMA requests by setting DCR[START]. Each channel can be
programmed to select one peripheral request from a set of 16 possible request inputs. The
channels support cycle-steal and continuous transfer modes; see
(Cycle-Steal and Continuous
The DMA controller supports dual-address transfers using its bus master connection to
the system bus. The DMA channels support transfers up to 32 data bits in size and have
the same memory map addressibility as the processor.
Freescale Semiconductor, Inc.
• Dual-address transfers via 32-bit master connection to the system bus
• Data transfers in 8-, 16-, or 32-bit blocks
• Continuous-mode or cycle-steal transfers from software or peripheral initiation
• One programmable input selected from 16 possible peripheral requests per channel
• Automatic hardware acknowledge/done indicator from each channel
• Independent source and destination address registers
• Optional modulo addressing and automatic updates of source and destination
• Independent transfer sizes for source and destination
• Optional auto-alignment feature for source or destination accesses
• Optional automatic single or double channel linking
• Programming model accessed via 32-bit slave peripheral bus
• Channel arbitration on transfer boundaries using fixed priority scheme
addresses
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Modes).
Preliminary
Transfer Requests
Chapter 19 DMA Controller
413

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