mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1315

no-image

mcf51jf128

Manufacturer Part Number
mcf51jf128
Description
Mcf51jf128 Reference Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mcf51jf128VLH
Manufacturer:
MITSUBISHI
Quantity:
321
Part Number:
mcf51jf128VLH
Manufacturer:
FREESCALE
Quantity:
5 097
Part Number:
mcf51jf128VLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mcf51jf128VLH
Manufacturer:
FREESCALE
Quantity:
5 097
The following figure shows a conflict between the ACK pulse and the sync request pulse.
This conflict could occur if a pod device is connected to the target BKGD pin and the
target is already executing a BDC command. Consider that the target CPU is executing a
pending BDC command at the exact moment the pod is being connected to the BKGD
pin. In this case, an ACK pulse is issued at the same time as the SYNC command. In this
case there is an electrical conflict between the ACK speedup pulse and the sync pulse.
Because this is not a probable situation, the protocol does not prevent this conflict from
happening.
The hardware handshake protocol is enabled by the ACK_ENABLE command and
disabled by the ACK_DISABLE command. It also allows for pod devices to choose
between the hardware handshake protocol or the software protocol that monitors the
XCSR status byte. The ACK_ENABLE and ACK_DISABLE commands are:
Freescale Semiconductor, Inc.
(TARGET MCU)
(TARGET MCU)
DRIVES SYNC
DRIVES SYNC
TARGET MCU
TARGET MCU
BKGD PIN
TO BKGD PIN
TO BKGD PIN
BDC CLOCK
BDC CLOCK
DRIVES TO
DRIVES TO
BKGD PIN
BKGD PIN
BKGD PIN
BKGD PIN
HOST
HOST
READ_MEM.B
Figure 50-9. ACK Abort Procedure at the Command Level
READ_MEM.B CMD
IS ABORTED BY THE SYNC REQUEST
(NOT TO SCALE)
Figure 50-10. ACK Pulse and SYNC Request Conflict
HOST
MCF51JF128 Reference Manual, Rev. 2, 03/2011
ADDRESS[23-0]
TARGET
HOST SYNC REQUEST PULSE
HOST SYNC REQUEST PULSE
BDC DECODES
AND CPU TRYS TO EXECUTE
THE READ_MEM.B CMD
ACK PULSE
ACK PULSE
16 CYCLES
16 CYCLES
HOST AND TARGET
HOST AND TARGET
DRIVE TO BKGD PIN
DRIVE TO BKGD PIN
AT LEAST 128 CYCLES
AT LEAST 128 CYCLES
Preliminary
READ_XCSR_BYTE
ELECTRICAL CONFLICT
ELECTRICAL CONFLICT
HIGH-IMPEDANCE
HIGH-IMPEDANCE
SYNC RESPONSE
FROM THE TARGET
(NOT TO SCALE)
HOST
TARGET
NEW BDC COMMAND
NEW BDC COMMAND
HOST
SPEEDUP PULSE
SPEEDUP PULSE
Chapter 50 Debug
TARGET
1315

Related parts for mcf51jf128