mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1154

no-image

mcf51jf128

Manufacturer Part Number
mcf51jf128
Description
Mcf51jf128 Reference Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mcf51jf128VLH
Manufacturer:
MITSUBISHI
Quantity:
321
Part Number:
mcf51jf128VLH
Manufacturer:
FREESCALE
Quantity:
5 097
Part Number:
mcf51jf128VLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mcf51jf128VLH
Manufacturer:
FREESCALE
Quantity:
5 097
Reset
Memory Map and Registers
44.3.13 SAI Receive Configuration 3 Register (I2Sx_RCR3)
This register cannot be altered when the receive enable bit is set.
Addresses: I2S0_RCR3 is FFFF_8200h base + 8Ch offset = FFFF_828Ch
1154
Bit
W
R
CLKMODE
Reserved
Reserved
31
0
31–28
27–26
23–8
Field
BCP
BCD
7–0
DIV
25
24
30
0
29
0
28
0
This read-only bitfield is reserved and always has the value zero.
Clocking mode
When configured for external bit clock, this field configures for asynchronous or synchronous operation.
When configured for internal bit clock, this field selects the Audio Master Clock used to generate the
internal bit clock. See the Chip Configuration details for information about the availability of these options.
00
01
10
11
Bit clock polarity
Configures the polarity of the bit clock.
0
1
Bit clock direction
Configures the direction of the bit clock.
0
1
This read-only bitfield is reserved and always has the value zero.
Bit clock divide
Divides down the audio master clock to generate the bit clock when configured for an internal bit clock.
The division value is (DIV + 1) * 2.
27
0
Bit Clock is active high (drive outputs on rising edge and sample inputs on falling edge).
Bit Clock is active low (drive outputs on falling edge and sample inputs on rising edge).
Bit clock is generated externally (slave mode).
Bit clock is generated internally (master mode).
26
0
Asynchronous mode (external bit clock) or Bus Clock selected (internal bit clock).
Synchronous with transmitter (external bit clock) or Master Clock 1 selected (internal bit clock).
Synchronous with another SAI receiver (external bit clock) or Master Clock 2 selected (internal bit
clock).
Synchronous with another SAI transmitter (external bit clock) or Master Clock 3 selected (internal bit
clock).
25
0
24
0
0
MCF51JF128 Reference Manual, Rev. 2, 03/2011
23
0
22
0
I2Sx_RCR2 field descriptions
21
0
20
0
19
0
18
0
Preliminary
17
0
16
0
15
0
Description
14
0
13
0
12
0
11
0
10
0
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
4
0
0
3
WDFL
0
2
0
1
0
0

Related parts for mcf51jf128