mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 423

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
Reserved
Reserved
SSIZE
27–25
24–23
21–20
DINC
EINT
SINC
ERQ
Field
CS
AA
31
30
29
28
22
19
Enable interrupt on completion of transfer
Determines whether an interrupt is generated by completing a transfer or by the occurrence of an error
condition.
0
1
Enable peripheral request
CAUTION: Be careful: a collision can occur between the START bit and D_REQ when the ERQ bit is 1.
0
1
Cycle steal
0
1
Auto-align
AA and SIZE bits determine whether the source or destination is auto-aligned; that is, transfers are
optimized based on the address and size.
0
1
This read-only bitfield is reserved and always has the value zero.
This bitfield is reserved.
CAUTION: Must be written as zero; otherwise, undefined behavior results.
Source increment
Controls whether the source address increments after each successful transfer.
0
1
Source size
Determines the data size of the source bus cycle for the DMA controller.
00
01
10
11
Destination increment
No interrupt is generated.
Interrupt signal is enabled.
Peripheral request is ignored.
Enables peripheral request, defined by the appropriate REQC[DMACn] field, to initiate transfer. A
software-initiated request (setting the START bit) is always enabled.
DMA continuously makes read/write transfers until the BCR decrements to 0.
Forces a single read/write transfer per request.
Auto-align disabled
If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise,
destination accesses are auto-aligned. Source alignment takes precedence over destination
alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of
DINC or SINC.
No change to SAR after a successful transfer.
The SAR increments by 1, 2, 4 as determined by the transfer size.
Longword
Byte
Word
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel
activation)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
DMA_DCRn field descriptions
Table continues on the next page...
Preliminary
Description
Chapter 19 DMA Controller
423