mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 448

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
448
FLL Engaged External
(FEE)
FLL Bypassed Internal
(FBI)
FLL Bypassed External
(FBE)
Mode
FLL engaged external (FEE) mode is entered when all the following conditions occur:
In FEE mode, MCGOUT is derived from the FLL clock (DCOCLK) that is controlled by the external
reference clock. The FLL loop will lock the DCO frequency to the FLL factor, as selected by
C4[DRST_DRS] and C4[DMX32] bits, times the external reference frequency, as specified by the
C1[FRDIV] and C2[RANGE]. Refer to the C4[DMX32] bit description for more details. In FEE mode,
the PLL is disabled in a low-power state unless C5[PLLCLKEN] is set.
FLL bypassed internal (FBI) mode is entered when all the following conditions occur:
In FBI mode, the MCGOUT clock is derived either from the slow (32 kHz IRC) or fast (2 MHz IRC)
internal reference clock, as selected by the C2[IRCS] bit. The FLL is operational but its output is not
used. This mode is useful to allow the FLL to acquire its target frequency while the MCGOUT clock
is driven from the C2[IRCS] selected internal reference clock. The FLL clock (DCOCLK) is
controlled by the slow internal reference clock, and the DCO clock frequency locks to a
multiplication factor, as selected by the C4[DRST_DRS] and C4[DMX32] bits, times the internal
reference frequency. Refer to the C4[DMX32] bit description for more details. In FBI mode, the PLL
is disabled in a low-power state unless C5[PLLCLKEN] is set.
FLL bypassed external (FBE) mode is entered when all the following conditions occur:
In FBE mode, the MCGOUT clock is derived from the external reference clock. The FLL is
operational but its output is not used. This mode is useful to allow the FLL to acquire its target
frequency while the MCGOUT clock is driven from the external reference clock. The FLL clock
(DCOCLK) is controlled by the external reference clock, and the DCO clock frequency locks to a
multiplication factor, as selected by the C4[DRST_DRS] and C4[DMX32] bits, times the divided
external reference frequency. Refer to the C4[DMX32] bit description for more details. In FBI mode
the PLL is disabled in a low-power state unless PLLCLKEN is set.
Description
Table 20-14. MCG Modes of Operation (continued)
• C1[CLKS] bits are written to 00
• C1[IREFS] bit is written to 0
• C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25
• C6[PLLS] bit is written to 0
• C1[CLKS] bits are written to 01
• C1[IREFS] bit is written to 1
• C6[PLLS] is written to 0
• C2[LP] is written to 0
• C1[CLKS] bits are written to 10
• C1[IREFS] bit is written to 0
• C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25
• C6[PLLS] bit is written to 0
• C2[LP] is written to 0
kHz to 39.0625 kHz
kHz to 39.0625 kHz.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
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Preliminary
Freescale Semiconductor, Inc.