mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 353

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mcf51jf128

Manufacturer Part Number
mcf51jf128
Description
Mcf51jf128 Reference Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Addresses: INTC_LVL1IACK is FFFF_FFC0h base + 24h offset = FFFF_FFE4h
15.5 Functional Description
The basic operation of the CF1_INTC is detailed in the preceding sections. This section
describes special rules applicable to non-maskable level seven interrupt requests and the
module's interfaces.
15.5.1 Handling of Non-Maskable Level 7 Interrupt Requests
In this context of this discussion, the non-maskable level 7 interrupt requests refer only to
the masking capability provided by the processor's SR[I] field. The ability to mask
individual interrupt requests using the interrupt controller's IMR is always available,
regardless of the level of a particular interrupt request.
The CPU treats level 7 interrupts as non-maskable, edge-sensitive requests, while levels 1
through 6 are maskable, level-sensitive requests. As a result of this definition, level 7
interrupt requests are a special case. The edge-sensitive nature of these requests means
the encoded 3-bit level input from the CF1_INTC to the V1 ColdFire core must change
state before the CPU detects an interrupt. A non-maskable interrupt (NMI) is generated
Freescale Semiconductor, Inc.
Reserved
VECN
Reset
Field
Read
6–0
Write
7
Bit
INTC_LVL2IACK is FFFF_FFC0h base + 28h offset = FFFF_FFE8h
INTC_LVL3IACK is FFFF_FFC0h base + 2Ch offset = FFFF_FFECh
INTC_LVL4IACK is FFFF_FFC0h base + 30h offset = FFFF_FFF0h
INTC_LVL5IACK is FFFF_FFC0h base + 34h offset = FFFF_FFF4h
INTC_LVL6IACK is FFFF_FFC0h base + 38h offset = FFFF_FFF8h
INTC_LVL7IACK is FFFF_FFC0h base + 3Ch offset = FFFF_FFFCh
This read-only bit is reserved and always has the value zero.
Vector number
Indicates the appropriate vector number.
It is the highest priority request within the specified level-n. If there are no pending requests within the
level, VECN is 0x18 (24) to signal a spurious interrupt.
7
0
0
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
INTC_LVLnIACK field descriptions
0
5
Preliminary
1
4
Description
VECN
1
3
Chapter 15 Interrupt Controller (INTC)
0
2
0
1
0
0
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