mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 597

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

26.6.3.1 Coprocessor No Operation (CNOP)
The CNOP command is the coprocessor no-op defined by the ColdFire coprocessor
definition for synchronization. It is not actually issued to the coprocessor from the core.
26.6.3.2 Load Register (LDR)
The LDR command loads CAx with the source data specified by <ea>.
26.6.3.3 Store Register (STR)
The STR command returns the value of CAx to the destination specified by <ea>.
26.6.3.4 Add to Register (ADR)
The ADR command adds the source operand specified by <ea> to CAx and stores the
result in CAx.
26.6.3.5 Reverse and Add to Register (RADR)
The RADR command performs a byte reverse on the source operand specified by <ea>,
adds that value to CAx, and stores the result in CAx. This table shows an example.
Freescale Semiconductor, Inc.
cp0ld
Type
cp0ld.l
cp0ld.l
cp0st.l
cp0ld.l
cp0ld.l
Command
Name
#CNOP
<ea>,#LDR+CAx
<ea>,#STR+CAx
<ea>,#ADR+CAx
<ea>,#RADR+CAx
ILL
Illegal Command
Table 26-14. CAU Commands (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Description
8
Preliminary
7
6
5
0x1F0
Chapter 26 Cryptographic Acceleration Unit (CAU)
CMD
4
3
2
1
0
0x1→CASR[IC]
Operation
597