mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 122

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Timers
3.9.4.2 LPTMR pin connections
Each LPTMR module has one 16-bit channel.
There are three LPTMR pins: LPTMR_ALT1, LPTMR_ALT2, and LPTMR_ALT3.
Each of these are connected to both LPTMR0 and LPTMR1 and can be selected by each
module's CSR[TPS] field with the settings 01, 10, and 11, respectively.
The CMP output pin can also be connected to both LPTMR0 and LPTMR1 by setting
each module's CSR[TPS] field to 00. This configuration allows pulse counting of the
CMP output.
3.9.4.3 LPTMR clock options
Each module's PSR[PCS] field controls the selection of external clock options. For both
LPTMR0 and LPTMR1:
The effect of setting PSR[PCS] to 11 differs for the two LPTMRs:
3.9.4.4 LPTMR register reset
All LPTMR registers are reset by Chip POR not VLLS and by POR Only, which triggers
Chip POR not VLLS. LPTMR registers are unaffected by other reset types. For
information about the various reset types on this chip, refer to the
3.9.5 Carrier Modulator Transmitter (CMT) Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
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• Setting PSR[PCS] to 00 selects the MCGIRCLK internal reference clock (not
• Setting PSR[PCS] to 01 selects the internal 1 kHz LPO clock.
• Setting PSR[PCS] to 10 selects ERCLK1 (low), the 32.768 kHz clock from OSC1.
• For LPTMR0, this setting selects the bus clock.
• For LPTMR1, this setting selects ERCLK2.
available in low leakage power modes).
This connection is optimized for minimal power consumption in stop modes.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Reset
Freescale Semiconductor, Inc.
details.