mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 845

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

If the channel input does not have a filter enabled, then the input signal is always delayed
3 rising edges of the system clock (two rising edges to the synchronizer plus one more
rising edge to the edge detector). In other words, the CHnF bit is set on the third rising
edge of the system clock after a valid edge occurs on the channel input.
37.4.4.1 Filter for Input Capture Mode
The filter function is only available on channels 0, 1, 2, and 3.
Firstly the input signal is synchronized by the system clock. Following synchronization,
the input signal enters the filter block (see the following figure). When there is a state
change in the input signal, the 5-bit counter is reset and starts counting up. As long as the
new state is stable on the input, the counter continues to increment. If the 5-bit counter
overflows (the counter exceeds the value of the CHnFVAL[3:0] bits), the state change of
the input signal is validated. It is then transmitted as a pulse edge to the edge detector.
Freescale Semiconductor, Inc.
system clock
channel (n) input
• Input capture mode is only available with (CNTINH:L =
• Input capture mode with (CNTINH:L ≠ 0x0000) is not
D
0x0000).
recommended and its results are not guaranteed.
CLK
synchronizer
Q
D
MCF51JF128 Reference Manual, Rev. 2, 03/2011
* NOTE: Filtering function is only available in the inputs of channel 0, 1, 2, and 3
CLK
Figure 37-150. Input Capture Mode
Q
Filter*
Preliminary
Note
enabled?
is filter
0
1
detector
falling edge
rising edge
edge
edge selected?
edge selected?
0
0
was falling
was rising
1
1
0
0
CHnIE
CHnF
Chapter 37 FlexTimer (FTM)
CnVH:L[15:0]
FTM counter
channel (n) interrupt
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