mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1150

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Registers
44.3.10 SAI Receive Control Register (I2Sx_RCSR)
Addresses: I2S0_RCSR is FFFF_8200h base + 80h offset = FFFF_8280h
1150
Reset
Reset
Bit
Bit
W
W
R
R
STOPE
DBGE
Field
BCE
RE
31
30
29
28
RE
31
15
0
0
30
14
0
0
0
Receiver enable
Enables/disables the receiver. When software clears this bit, the receiver remains enabled (and this bit
remains set) until the end of the current frame.
0
1
Stop enable
Configures receiver operation in Stop mode. This bit is ignored and the receiver is disabled in all low-
leakage stop modes.
0
1
Debug enable
Enables/disables receiver operation in debug mode. The receive bit clock is not affected by debug mode.
0
1
Bit Clock enable
Enables the receive bit clock, separately from the receive enable. This bit is automatically set whenever
the receive enable is set. When software clears this bit, the receive bit clock remains enabled (and this bit
remains set) until the end of the current frame.
0
1
Receiver is disabled.
Receiver is enabled, or receiver has been disabled and not end of frame.
Receiver disabled in stop mode.
Receiver enabled in stop mode.
Receiver is disabled in debug mode, after completing the current frame.
Receiver is enabled in debug mode.
Receive bit clock is disabled
Receive bit clock is enabled
29
13
0
0
BCE
28
12
0
0
MCF51JF128 Reference Manual, Rev. 2, 03/2011
SEIE FEIE
27
11
0
0
I2Sx_RCSR field descriptions
0
Table continues on the next page...
26
10
0
0
FR
25
0
0
0
9
Preliminary
SR
24
0
0
8
Description
23
0
0
7
22
0
0
0
0
6
21
0
0
5
WSF
w1c
20
0
0
4
Freescale Semiconductor, Inc.
SEF
w1c
19
0
0
0
3
FEF
w1c
18
0
0
2
FWF
17
0
0
1
FRF
16
0
0
0