mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1158

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

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Memory Map and Registers
44.3.17 SAI Receive FIFO Register (I2Sx_RFR)
The MSB of the read pointer and write pointer is used to distinguish between FIFO full
and empty conditions. If the read and write pointers are identical then the FIFO is empty.
If the read and write pointers are identical except for the MSB then the FIFO is full.
Addresses: I2S0_RFR is FFFF_8200h base + C0h offset = FFFF_82C0h
44.3.18 SAI Receive Mask Register (I2Sx_RMR)
This register is double-buffered and updates when the receive enable bit is first set and
then at the end of each frame. This allows the masked words in each frame to change
from frame to frame.
Addresses: I2S0_RMR is FFFF_8200h base + E0h offset = FFFF_82E0h
1158
Bit
Bit
W
W
R
R
Reserved
Reserved
31
31
0
0
31–19
18–16
WFP
15–3
Field
RFP
2–0
30
30
0
0
29
29
0
0
28
28
0
0
This read-only bitfield is reserved and always has the value zero.
Write FIFO pointer
FIFO write pointer for receive data channel.
This read-only bitfield is reserved and always has the value zero.
Read FIFO pointer
FIFO read pointer for receive data channel.
27
27
0
0
26
26
0
0
25
25
0
0
0
24
24
0
0
0
MCF51JF128 Reference Manual, Rev. 2, 03/2011
23
23
0
0
22
22
0
0
21
21
0
I2Sx_RFR field descriptions
0
20
20
0
0
19
19
0
0
18
18
0
0
Preliminary
WFP
17
17
0
0
16
16
0
0
15
15
0
0
Description
14
14
0
0
13
13
0
0
12
12
0
0
11
11
0
0
10
10
0
0
0
0
0
9
9
RWM
0
0
8
8
Freescale Semiconductor, Inc.
0
0
7
7
0
0
6
6
0
0
5
5
4
0
4
0
0
0
3
3
0
0
2
2
RFP
0
0
1
1
0
0
0
0