HYB39S256400T-10 SIEMENS [Siemens Semiconductor Group], HYB39S256400T-10 Datasheet - Page 12

• Manufacturer Part Number: HYB39S256400T-10
• Description: 256 MBit Synchronous DRAM
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

terminate once the burst length has been reached. In other words, unlike burst length of 2, 3 or 8,
full page burst continues until it is terminated using another command.
Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column
address are possible once the RAS cycle latches the sense amplifiers. The maximum
refresh interval time limits the number of random column accesses. A new burst access can be
done even before the previous burst ends. The interrupt operation at every clock cycle is supported.
When the previous burst is interrupted, the remaining addresses are overridden by the new address
with the full burst length. An interrupt which accompanies an operation change from a read to a write
is possible by exploiting DQM to avoid bus contention.
When two or more banks are activated sequentially, interleaved bank read or write operations are
possible. With the programmed burst length, alternate access and precharge operations on two or
more banks can realize fast serial data access modes among many different pages. Once two or
more banks are activated, column to column interleave operation can be done between different
pages.
Burst Length and Sequence
Burst
Length
2
4
8
Refresh Mode
SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS
-before-RAS refresh of conventional DRAMs. All of banks must be precharged before applying any
refresh mode. An on-chip address counter increments the word and the bank addresses and no
bank information is required for both refresh modes.
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are
held high at a clock timing. The mode restores word line after the refresh and no external precharge
command is necessary. A minimum
refresh mode. The same rule applies to any access command after the automatic refresh operation.
Semiconductor Group
Starting Address
(A2 A1 A0)
x00
x01
x10
x11
000
001
010
011
100
101
110
111
xx0
xx1
Sequential Burst Addressing
0
1
2
3
4
5
6
7
t
RC
1
2
3
4
5
6
7
0
time is required between two automatic refreshes in a burst
2
3
4
5
6
7
0
1
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
(decimal)
0, 1
1, 0
3
4
5
6
7
0
1
2
12
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
256 MBit Synchronous DRAM
7
0
1
2
3
4
5
6
HYB 39S256400/800/160T
Interleave Burst Addressing
0
1
2
3
4
5
6
7
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
(decimal)
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
3
2
1
0
7
6
5
4
0, 1
1, 0
4
5
6
7
0
1
2
3
1998-10-01
5
4
7
6
1
0
3
2
t
RAS
6
7
4
5
2
3
0
1
or the
7
6
5
4
3
2
1
0