HYB39S256400T-10 SIEMENS [Siemens Semiconductor Group], HYB39S256400T-10 Datasheet - Page 8
HYB39S256400T-10
Manufacturer Part Number
HYB39S256400T-10
Description
256 MBit Synchronous DRAM
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
1.HYB39S256400T-10.pdf
(56 pages)
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Signal Pin Description
Pin
DQM
LDQM
UDQM
V
V
V
V
Semiconductor Group
DD
SS
DDQ
SSQ
,
Type
Input
Supply –
Supply –
Signal Polarity Function
Pulse
Active
High
–
–
The Data Input/Output mask places the DQ buffers in a high
impedance state when sampled high. In Read mode, DQM
has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a
latency of zero and operates as a word mask by allowing
input data to be written if it is low but blocks the write
operation if DQM is high.
One DQM input it present in 4 and 8 SDRAMs, LDQM and
UDQM controls the lower and upper bytes in 16 SDRAMs.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to
provide improved noise immunity.
8
256 MBit Synchronous DRAM
HYB 39S256400/800/160T
1998-10-01
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