HYB39S256400T-10 SIEMENS [Siemens Semiconductor Group], HYB39S256400T-10 Datasheet - Page 9

• Manufacturer Part Number: HYB39S256400T-10
• Description: 256 MBit Synchronous DRAM
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the truth table for the operation commands.
Operation
Bank Active
Bank Precharge
Precharge All
Write
Write with Auto Precharge Active
Read
Read with Auto Precharge Active
Mode Register Set
No Operation
Burst Stop
Device Deselect
Auto Refresh
Self Refresh Entry
Self Refresh Exit
Clock Suspend Entry
Power Down Entry
(Precharge or active
standby)
Clock Suspend Exit
Power Down Exit
Data Write/Output Enable
Data Write/Output Disable Active
Notes
1. V = Valid, X = Don’t Care, L = Low Level, H = High Level.
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock
3. This is the state of the banks designated by BS0, BS1 signals.
4. Device state is Full Page Burst operation.
5. Power Down Mode can not entry in the burst cycle. When this command assert in the burst mode
Semiconductor Group
before the commands are provided.
cycle device is clock suspend mode.
Device
State
Idle
Any
Any
Active
Active
Idle
Any
Active
Any
Idle
Idle
Idle
(Self
Refr.)
Active
Idle
Active
Active
Any
(Power
Down)
Active
3
3
3
3
3
4
5
CKE
n-1
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
CKE
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
X
X
n
L
L
L
DQM
9
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
BS0
BS1
V
V
X
V
V
V
V
V
X
X
X
X
X
X
X
X
X
X
X
X
256 MBit Synchronous DRAM
AP =
A10
V
H
H
H
V
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
HYB 39S256400/800/160T
Addr
V
X
X
V
V
V
V
V
X
X
X
X
X
X
X
X
X
X
X
X
CS
H
H
X
H
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS
H
H
H
H
H
H
X
X
H
X
X
H
X
X
H
X
X
L
L
L
L
L
L
CAS
1998-10-01
H
H
H
H
H
X
X
H
X
X
H
X
X
H
X
X
L
L
L
L
L
L
L
WE
H
H
H
H
X
H
H
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L