HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 151

IC SUPERH MCU FLASH 256K 112QFP

HD64F7144F50V

Manufacturer Part Number
HD64F7144F50V
Description
IC SUPERH MCU FLASH 256K 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheets

Specifications of HD64F7144F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Note:
7.2.4
The user break control register (UBCR) is a 16-bit readable/writable register that enables or
disables user break interrupts.
Bit
3
2
1
0
Bit
15 to 1 —
0
*
Bit Name Initial Value
RW1
RW0
SZ1
SZ0
Bit Name Initial Value
UBID
User Break Control Register (UBCR)
When breaking on an instruction fetch, clear the SZ0 bit to 0. All instructions are
considered to be accessed in word-size (even when there are instructions in on-chip
memory and two instruction fetches are performed simultaneously in one bus cycle).
Operand size is word for instructions or determined by the operand size specified for
the CPU/DTC, DMAC data access. It is not determined by the bus width of the space
being accessed.
0
0
0
0
All 0
0
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Description
Read/Write Select 1 and 0
These bits select whether to break on read and/or
write cycles
00: No user break interrupt occurs
01: Break on read cycles
10: Break on write cycles
11: Break on both read and write cycles
Operand Size Select 1 and 0*
These bits select operand size as a break condition.
00: Operand size is not a break condition
01: Break on byte access
10: Break on word access
11: Break on longword access
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
User Break Disable
Enables or disables user break interrupt request
generation in the event of a user break condition
match.
0: User break interrupt request is enabled
1: User break interrupt request is disabled
Rev.4.00 Mar. 27, 2008 Page 105 of 882
7. User Break Controller (UBC)
REJ09B0108-0400

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