HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 173
HD64F7144F50V
Manufacturer Part Number
HD64F7144F50V
Description
IC SUPERH MCU FLASH 256K 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Specifications of HD64F7144F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Normal Mode: Performs the transfer of one byte, one word, or one longword for each activation.
The total transfer count is 1 to 65536. Once the specified number of transfers have ended, a CPU
interrupt can be requested. Table 8.2 lists the register functions in normal mode. Figure 8.6 shows
a memory map in normal mode.
Table 8.2
Repeat Mode: Performs the transfer of one byte, one word, or one longword for each activation.
Either the transfer source or transfer destination is designated as the repeat area. Table 8.3 lists the
register functions in repeat mode. From 1 to 256 transfers can be specified. Once the specified
number of transfers have ended, the initial state of the transfer counter and the address register
specified as the repeat area is restored, and transfer is repeated. In repeat mode the transfer counter
value does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0.
Figure 8.7 shows a memory map in repeat mode.
Register
DTMR
DTCRA
DTSAR
DTDAR
Normal Mode Register Functions
DTSAR
Function
Operation mode
control
Transfer count
Transfer source
address
Transfer destination
address
Figure 8.6 Memory Mapping in Normal Mode
When DTCRA is other than 1
DTMR
DTCRA – 1
Increment/decrement/fixed
Increment/decrement/fixed
Values Written Back upon Transfer Information Write
Transfer
Rev.4.00 Mar. 27, 2008 Page 127 of 882
8. Data Transfer Controller (DTC)
When DTCRA is 1
Increment/decrement/fixed
Increment/decrement/fixed
DTMR
DTCRA – 1 (= H'0000)
DTDAR
REJ09B0108-0400
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