HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 925

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

A/D conversion time............................... 550
A/D converter ......................................... 541
Absolute maximum ratings ..................... 767
Activation by interrupt............................ 134
Activation by software............................ 134
Address error exception processing .......... 68
Address map ..................................... 51, 141
Addressing modes..................................... 25
Advanced user debugger (AUD) ............ 705
Asynchronous serial communication ...... 426
Auto-request mode.................................. 182
Block configuration ................................ 663
Block transfer mode................................ 129
Boot mode............................................... 671
Branch trace mode .................................. 708
Buffer operation...................................... 266
Burst mode.............................................. 195
Bus arbitration ........................................ 161
Bus masters............................................. 161
Bus release state........................................ 46
Bus state controller (BSC) ...................... 137
Byte data ................................................... 19
Cascaded operation ................................. 269
Chain transfer.......................................... 130
Clock mode............................................... 48
Clock pulse generator ............................... 53
Clocked synchronous communication .... 443
Compare match....................................... 261
Compare match timer (CMT) ................. 559
Complementary PWM mode .................. 285
Continuous scan mode ............................ 549
Control registers........................................ 17
CPU .......................................................... 15
Crystal oscillator....................................... 55
Cycle-steal mode .................................... 195
Data format in registers............................. 19
Data formats.............................................. 19
Data formats in memory ........................... 19
Index
Data transfer controller (DTC)................113
Delayed branch instructions......................21
Direct memory access controller (DMAC)
DTC vector addresses .............................124
Dual address mode ..................................190
Effective address .......................................25
Electrical characteristics..........................767
Error Protection.......................................681
Exception processing ................................61
Exception processing state ........................46
Exception processing vector table.............63
External clock input ..................................56
External request mode.............................182
Fixed mode..............................................184
Flash memory..........................................657
Flash memory emulation in RAM...........674
Free-running counters .............................260
Function for detecting the oscillator halt...57
Functions of multiplexed pins.................569
General illegal instructions .......................72
General registers (Rn) ...............................15
Global base register (GBR).......................18
Hardware protection................................680
I/O ports ..................................................633
I
I
Illegal slot instructions ..............................72
Immediate data format ..............................20
Input capture function .............................263
Internal clock ............................................53
Interrupt controller (INTC) .......................77
Interrupt exception processing ..................70
Interrupt response time..............................96
Interval timer mode .................................386
IRQ interrupts .....................................84, 87
Longword data ..........................................19
Manual reset..............................................66
................................................................167
2
2
C bus format .........................................493
C bus interface......................................467
Rev.4.00 Mar. 27, 2008 Page 879 of 882
REJ09B0108-0400
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